vi March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
9.3 Programmer Model.......................................................... .............................................................2
9.3.1 INTCTL................................. ....................................................................................... 3
9.3.2 INTSRC...... ....................................................................... .......................................... 4
9.3.3 INTSTR..................................................................................... ...................................5
10 External Bus .............................................................................................1
10.1 General Description................................................... ...................................................................1
10.2 Signal Description............................................................................... ..........................................3
10.2.1 Request Bus......................... ....................................................................................... 4
10.2.1.1 Intel® 80200 Processor Use of the Request Bus............................. .........4
10.2.2 Data Bus............................................................... .......................................................6
10.2.3 Critical Word First................. ....................................................................................... 7
10.2.4 Configuration Pins ....................................................................................................... 8
10.2.5 Multimaster Support.................................................................................................. ...9
10.2.6 Abort..................................... ....................................................................... .............. 11
10.2.7 ECC...................................... ....................................................................... .............. 12
10.2.8 Big Endian System Configuration......................... .....................................................13
10.3 Examples................................................................... ................................................................. 14
10.3.1 Simple Read Word..................................................................................................... 14
10.3.2 Read Burst, No Critical Word First...................................................................... .......15
10.3.3 Read Burst, Critical Word First Data Return.......................................... ....................16
10.3.4 Word Write...................................................................................... ...........................17
10.3.5 Two Word Coalesced Write.................................. .....................................................18
10.3.5.1 Write Burst................................................................... ...........................19
10.3.6 Write Burst, Coalesced......................................... .....................................................20
10.3.7 Pipelined Accesses.................................................................................................... 21
10.3.8 Locked Access........................................................................................................... 22
10.3.9 Aborted Access.......................................................................................................... 23
10.3.10 Hold...... ..................................................................................................................... 24
11 Bus Controller ..........................................................................................1
11.1 Introduction......................................................... .......................................................................... 1
11.2 ECC................................................. ....................................................................... ...................... 1
11.3 Error Handling ........................................................................................................................... ...2
11.3.1 Bus Aborts............................ ....................................................................................... 2
11.3.2 ECC Errors .................................................................................................................. 3
11.4 Programmer Model.......................................................... .............................................................5
11.4.1 BCU Control Registers ................................................................................................ 5
11.4.2 ECC Error Registers............................................. .......................................................9
12 Performance Monitoring..........................................................................1
12.1 Overview............................................................................................. ..........................................1
12.2 Clock Counter (CCNT; CP14 - Register 1)............................ .......................................................2
12.3 Performance Count Registers (PMN0 - PMN1; CP14 - Register 2 and 3, Respectively) .............3
12.3.1 Extending Count Duration Beyond 32 Bits .................................................................. 3
12.4 Performance Monitor Control Register (PMNC) ........................................................................... 4
12.4.1 Managing PMNC ......................................................................................................... 5
12.5 Performance Monitoring Events ................................................................................................... 6
12.5.1 Instruction Cache Efficiency Mode .............................................................................. 7
12.5.2 Data Cache Efficiency Mode ....................................................................................... 8