Intel 80200, Processor 11.3 Error Handling

11-2 March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Bus Controller
11.3 Error Handling
The BCU is able to detect and respond to two classes of errors: bus aborts and ECC errors.
Information about errors is captured in a set of programmer-accessible registers: ELOG0, ELOG1,
and ECAR0, ECAR1. The ELOGx registers log general information about an error, while the
ECARx registers capture the address associated with an error.
11.3. 1 Bus Aborts
A bus abort occurs when the Abort pin is asserted during an external bus transaction. This is
described in detail in Chapter10, “External Bus”. In response to a bus abort, the BCU causes an
exception in the currently running software. Note that if the exception raised is an External Data
Abort, then it is an imprecise exception -- it is not necessarily related to the instruction that just
executed.
The BCU attempts the additional response of logging the error into a register. If register ELOG0 is
not already being used to record an error, the BCU logs error information into registers ELOG0 and
ECAR0. If ELOG0 already has error information, but ELOG1 does not, the BCU use ELOG1 and
ECAR1 to log the error. If both ELOG0 and ELOG1 are in use, the BCU sets the error overflow bit
(registerBCUCTL, bit EV). A description of these registers is in Section 11.4.1 and
Section 11.4.2.
See Chapter2, “Programming Model”, for more discussion of Data Aborts.