Intel 80200, Processor Memory Management

Developer’s Manual March, 2003 3-1
Memory Management 3
This chapter describes the memory management unit implemented in the Intel® 80200 processor
based on Intel® XScale™ microarchitecture, and is compliant with the ARM* Architecture V5TE.
3.1 Overview
The Intel® 80200 processor implements the Memory Management Unit (MMU) Architecture
specified in the ARM Architecture Reference Manual. To accelerate virtual to physical address
translation, the Intel® 80200 processor uses both an instruction Translation Look-aside Buffer
(TLB) and a data TLB to cache the latest translations. Each TLB holds 32entries and is
fully-associative. Not only do the TLBs contain the translated addresses, but also the access rights
for memory references.
If an instruction or data TLB miss occurs, a hardware translation-table-walking mechanism is
invoked to translate the virtual address to a physical address. Once translated, the physical address
is placed in the TLB along with the access rights and attributes of the page or section. These
translations can also be locked down in either TLB to guarantee the performance of critical
routines.
The Intel® 80200 processor allows system software to associate various attributes with regions of
memory:
•cacheable
•bufferable
•line allocate policy
•write policy
•I/O
•mini Data Cache
•Coalescing
•ECC-Protected
See Section3 .2.2, “Memory Attributes” on page3-2 for a descri ption of page attributes and
Section 2.3.2, “New Page Attributes” on page2-9 to find out where these attributes have been
mapped in the MMU descriptors.
Note: The virtual address with which the TLBs are accessed may be remapped by the PID register. See
Section7.2.13, “Register 13: Process ID” on page 7-16 for a description of the PID re gister.