Intel 80200, Processor 13.16 Software Debug Notes/Errata

13-54 March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Software Debug
13.16 Software Debug Notes/Errata
1. Trace buffer message count value on data aborts:
LDR to non-PC that aborts gets counted in the exception message. But an LDR to the PC that
aborts does not get counted on exception message.
2. SW Note on data abort generation in Special Debug State.
1) Avoid code that could generate precise data aborts.
2) If this cannot be done, then handler needs to be written such that a memory access is
followed by 1 nops. In this case, certain memory operations must be avoided - LDM, STM,
STRD, LDC, SWP.
3. Data abort on Special Debug State:
When write-back is on for a memory access that causes a data abort, the base register is
updated with the write-back value. This is inconsistent with normal (non-SDS) behavior where
the base remains unchanged if write-back is on and a data abort occurs.
4. Trace Buffer wraps around and loses data in Halt Mode when configured for fill-once mode:
It is possible to overflow (and lose) data from the trace buffer in fill-once mode, in Halt Mode.
When the trace buffer fills up, it has space for 1 indirect branch message (5 bytes) and 1
exception message (1 byte).
If the trace buffer fills up with an indirect branch message and generates a trace buffer full
break at the same time as a data abort occurs, the data abort has higher priority, so the
processor first goes to the data abort handler. This data abort is placed into the trace buffer
without losing any data.
However, if another imprecise data abort is detected at the start of the data abort handler, it has
higher priority than the trace buffer full break, so the processor goes back to the data abort
handler. This 2nd data abort also gets written into the trace buffer. This causes the trace buffer
to wrap-around and one trace buffer entry is lost (oldest entry is lost). Additional trace buffer
entries can be lost if imprecise data aborts continue to be detected before the processor can
handle the trace buffer full break (which turns off the trace buffer).
This trace buffer overflow problem can be avoided by enabling vector traps on data aborts.
5. TXRXCTRL.RR prevents TX register from being updated (even if TXRXCTRL.TR is clear).
This is to be fixed on B-step.
The problem is that there is incorrect (and unnecessary) interaction between the RX ready
(RR) flag and writing the TX register. The debug handler looks at the TX ready bit before
writing to the TX register. If this bit is clear, then the handler should be able to write to the TX
register. However, in the current implementation even if the TR bit is clear, if the RR bit is set,
TX is unchanged when the handler writes to it. It is OK to prevent a write to TX when the TR
bit is set (since the host has not read the previous data in the TX, and we don’t want a write to
TX to overwrite previous data).
6. The TXRXCTRL.OV bit (overflow flag) does not get set during high-speed download when
the handler reads the RX register at the same time the debugger writes to it.
If the debugger writes to RX at the same time the handler reads from RX, the handler read
returns the newly written data and the previous data is lost. However, in this specific case, the
overflow flag does not get set, so the debugger is unaware that the download was not
successful.