Intel 80200, Processor 14.4 Instruction Latencies

Developer’s Manual March, 2003 14-3

Intel® 80200 Processor based on Intel® XScale™ Microarchitecture

Performance Considerations

14.4 Instruction Latencies

The latencies for all the instructions are shown in the following sections with respect to their

functional groups: branch, data processing, multiply, status register access, load/store, semaphore,

and coprocessor.

The following section explains how to read these tables.

•Issue Clock (cycle 0)

The first cycle when an instruction is decoded and allowed to proceed to further stages in the

execution pipeline (i.e., when the instruction is actually issued).

•Cycle Distance from A to B

The cycle distance from cycle A to cycle B is (B-A) -- that is, the number of cycles from the

start of cycle A to the start of cycle B. Example: the cycle distance from cycle3 to cycle 4 is

one cycle.

•Issue Latency

The cycle distance from the first issue clock of the current instruction to the issue clock of the

next instruction. The actual number of cycles can be influenced by cache-misses,

resource-dependency stalls, and resource availability conflicts.

•Result Latency

The cycle distance from the first issue clock of the current instruction to the issue clock of the

first instruction that can use the result without incurring a resource dependency stall. The

actual number of cycles can be influenced by cache-misses, resource-dependency stalls, and

resource availability conflicts

•Minimum Issue Latency (without Branch Misprediction)

The minimum cycle distance from the issue clock of the current instruction to the first possible

issue clock of the next instruction assuming best case conditions (i.e., that the issuing of the

next instruction is not stalled due to a resource dependency stall; the next instruction is

immediately available from the cache or memory interface; the current instruction does not

incur resource dependency stalls during execution that can not be detected at issue time; and if

the instruction uses dynamic branch prediction, correct prediction is assumed).

•Minimum Result Latency

The required minimum cycle distance from the issue clock of the current instruction to the

issue clock of the first instruction that can use the result without incurring a resource

dependency stall assuming best case conditions (i.e., that the issuing of the next instruction is

not stalled due to a resource dependency stall; the next instruction is immediately available

from the cache or memory interface; and the current instruction does not incur resource

dependency stalls during execution that can not be detected at issue time).

•Minimum Issue Latency (with Branch Misprediction)

The minimum cycle distance from the issue clock of the current branching instruction to the

first possible issue clock of the next instruction. This definition is identical to Minimum Issue

Latency except that the branching instruction has been mispredicted. It is calculated by adding

Minimum Issue Latency (without Branch Misprediction) to the minimum branch latency

penalty number from Table14-2, which is four cycles.