Intel® PXA255 Processor Developer’s Manual xiii
Contents
17.4.3 Autoflow Control.................................................................................................17-7
17.4.4 Auto-Baud-Rate Detection..................................................................................17-7
17.4.5 Slow Infrared Asynchronous Interface................................................................17-8
17.5 Register Descriptions.....................................................................................................17-10
17.5.1 Receive Buffer Register (RBR).........................................................................17-10
17.5.2 Transmit Holding Register (THR)......................................................................17-10
17.5.3 Divisor Latch Registers (DLL and DLH)............................................................17-10
17.5.4 Interrupt Enable Register (IER)........................................................................17-11
17.5.5 Interrupt Identification Register (IIR).................................................................17-13
17.5.6 FIFO Control Register (FCR)............................................................................17-15
17.5.7 Receive FIFO Occupancy Register (FOR).......................................................17-16
17.5.8 Auto-Baud Control Register (ABR)...................................................................17-17
17.5.9 Auto-Baud Count Register (ACR).....................................................................17-17
17.5.10Line Control Register (LCR)..............................................................................17-18
17.5.11Line Status Register (LSR) ...............................................................................17-19
17.5.12Modem Control Register (MCR) .......................................................................17-21
17.5.13Modem Status Register (MSR).........................................................................17-23
17.5.14Scratchpad Register (SCR) ..............................................................................17-24
17.5.15Infrared Selection Register (ISR)......................................................................17-24
17.6 Hardware UART Register Summary..............................................................................17-25
Figures
2-1 Block Diagram...........................................................................................................................2-2
2-2 Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF..........................................2-19
2-3 Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF..........................................2-20
3-1 Clocks Manager Block Diagram................................................................................................3-3
4-1 General-Purpose I/O Block Diagram.........................................................................................4-2
4-2 Interrupt Controller Block Diagram.......................................................... ................................4-21
4-3 PWMn Block Diagram.................................. ............................................ ... .............................4-39
4-4 Basic Pulse Width Waveform..................................................................................................4-43
5-1 DMAC Block Diagram................................................................................................................5-1
5-2 DREQ timing requirements........................................................................................................5-3
5-3 No-Descriptor Fetch Mode Channel State................................. ............................................ ....5-6
5-4 Descriptor Fetch Mode Channel State.......................................................................................5-8
5-5 Little Endian Transfers.............................................................................................................5-10
6-1 General Memory Interface Configuration...................................................................................6-2
6-2 SDRAM Memory System Example............................................................................................6-5
6-3 Static Memory System Example.......................................... ........................................... ... ........6-6
6-4 External to Internal Address Mapping Options........................................................................6-19
6-5 Basic SDRAM Timing Parameters...........................................................................................6-29
6-6 SDRAM_Read_diffbank_diffrow..............................................................................................6-29
6-7 SDRAM_read_samebank_diffrow...........................................................................................6-30
6-8 SDRAM_read_samebank_samerow.......................................................................................6-30
6-9 SDRAM_write..........................................................................................................................6-31
6-10 SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions.....................................................6-31
6-11 SDRAM 4-Beat Write / 4-Write Same Bank, Same Row....................................................... ..6-32
6-12 SMROM Read Timing Diagram Half-Memory Clock Frequency.............................................6-39
6-13 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode)..........................6-41