Intel® PXA255 Processor Developer’s Manual 7-25
LCD Controller
Beginning-of-Line Pixel Clock Wait Count (BLW) — used to specify the number of dummy
pixel clocks to insert at the beginning of each line or row of pixels. After the line clock for the
previous line has been negated, the value in BLW is used to count the number of pixel clocks to
wait before starting to output the first set of pixels in the next lin e. BLW generates a wait period
ranging from 1 to 256 pixel clock cyc l e s. BLW must be pr og ra m m e d wi t h the desired number of
pixel clocks minus one. L_PCLK does not toggle during these “dummy” pixel clock cycles in
passive display mode. It does toggle continuous ly in active display mode.
End-of-Line Pixel Clock Wait Count (E LW) — used to specify the number of “dummy” pixel
clocks to insert at the end of each line or row of pixels be fore pulsing the line clock pin. Once a
complete line of pixels is transmitted to the LCD driver, the value in E LW is used to count the
number of pixel clocks to wait before pulsing the line clock. ELW generates a wait perio d ranging
from 1 to 256 pixel clock cycles. ELW m ust be programmed with the desired number of pixel
clocks minus one. L_PCLK does not toggle during these dummy pixel clock cycles in passive
display mode. It does toggle continuously in active display mode.
Horizontal Sync Pulse Width (HSW) — specifies the pulse width (minus 1) of the line clock in
passive mode or the horizontal synchronization pulse in active mode. L_LCLK is asserted each
time a line is sent to the display and a programmable number of pixel clock wait states have
elapsed. When L_LCLK is asserted, the value in HSW is tra nsferr ed to a 6-bi t dow n coun ter, which
decrements at the programmed pixel clock frequency. When the counter reaches zero, L_LCLK is
negated. HSW can be programmed to generate a line cl oc k pulse width ranging from 1 to 64 pixel
clock periods.
The pixel clock does not toggle during the line cl ock pu lse in pas siv e dis pl ay mode bu t doe s to ggle
in active display mode. The polarity (active and inactive state) of the line clock pin is programmed
using the horizontal sync polarity (HSP) bit in LCCR3.
HSW must be programmed with the desired number of pixel clocks minus one.
Note: The term “pulse width” refers to the time which L_LCLK is asserted, rath er than the time for a
cycle of the line clock to occur.
Pixels Per Line (PPL) — used to specify the number of pixels in each line or row on the screen
(minus one). PPL is a 10-bit value that represents between 1 and 1024 pixels per line. It is
recommended not to exceed 640 pixels. It is used to count the number of pixel clocks that must
occur before the line clock can be asserted. As discussed in Section7.4.2, pixels per line must be
multiples of: 32 pixels for 1-bit pixels, 16 pixels for 2-bit pixels, 8 pixels for 4-bit pixels, 4 pixels
for 8-bit pixels, and 2 pixels for 16-bit pixels. The tw o special conditions are: 8-bits/pixel
monochrome screens with double-pixel-da ta mode and 8 or 16 bits/pixel passive color screens
require a multiple of 8 pixels for each line.
If the display used is not naturally a multiple of the above, “dummy” pixels must be added to each
line to keep the frame buffer alig ned in memor y. For example, if the display bei ng cont ro lled is 2 50
pixels wide and the pixel-size is 8-bits, the near es t grea ter mu lti ple of 8 is 256 . Pixel s per li ne mus t
be set to 255. 6 extra “dummy” pixel values must be added to the end of each line in the frame
buffer. The display being controlled must ignore the dummy pixel clocks at the end of each line.
This is a read/wri te register. Ignore reads from reserved bits . Write zeros to res erved bits.