Intel PXA255 8.5 FIFO Operation and Data Transfers, 8.6 Baud-Rate Generation

Intel® PXA255 Processor Developer’s Manual 8-7
Synchronous Serial Port Controller
8.5 FIFO Operation and Data Transfers
Transmit and receive serial data use independent FIFOs. FIFOs are filled or emptied by
programmed I/O or DMA bu rsts that the DMAC initi ates. Bursts may be 4 or 8 half-words in
length during transmission or reception .
8.5.1 Using Programmed I/O Data Transfers
Data words are 32 bits wide, but only 16-bit samples are transferred. Only the lower 2 bytes of a
32-bit word have valid data. The upper 2 bytes are not used and include invalid data that must be
discarded.
The processor can fill or empty FIFOs in response to an interrupt from the FIFO logic. Each FIFO
has a programmable interrupt threshold. When the threshold value is exceeded and an interrup t is
enabled, an interrupt that signals the CPU to empty the receive FIFO or refill the transmit FIFO is
generated.
The user can also poll the SSP Status Register (see Section8.7.4) to determine how many samples
are in a FIFO or whether the FIFO is full or empty.
8.5.2 Using DMA Data Transfers
The DMA controller can also be programmed to transfer data to and from the SSP’s FIFO’s. Refer
to Chapter 5, “DMA Controller” for instructions on programming the D M A c ha nnels.
The steps for the DMA programming model are:
1. Program the transmit/receive byte count (buffer length) and burst size.
2. Program the DMA request to channel map register for SSP.
3. Set the run bit in th e DMA control regist er.
4. Set the desired values in the SSP control registers.
5. Enable the SSP by setting the SSE bit in the SSP Control Register 0 (see Section 8.7.1).
6. Wait for both the DMA transmit and receive interrupt requests.
Note: If the transmit/receive byte count is not a multiple of the tra nsfer bu rst size, the user must check the
SSP Status Register (see Section 8.7.4) to determine if any data remains in the Receive FIFO.
8.6 Baud-Rate Generation
The baud (or bit-rate clock) is generated internally by dividing the internal clock (3.6864 MHz).
The internal clock is first divided by 2 and this divided clock feeds a programmable divider to
generate baud rates from 7.2kbps to 1.8432Mbps. Setting the External Clock Select (ECS) bit to 1
enables an external clock (SSPEXTCLK) to replace the 3.6864MHz standard internal clock. The
external clock is also divided by 2 before it is fed to the programmable divider.