Intel PXA255 14.5 Data Fo r mats

14-6 Intel® PXA255 Processor Developer’s Manual
Inter-Integrated-Circuit Sound (I2S) Controller
The BITCLK, as shown in Table 14- 2, is different for different sampling frequencies. If the
BITCLK is chosen as an output, the Audio Clock Divider Re gister divides the 147.46MHz PLL
clock to generate the SYSCLK. The SYSCLK is further div i ded by four to generate the BITCLK.
The sampling frequency is t he fre q ue n cy of the SYNC signal, which is gen e ra t e d by di viding the
BITCLK by 64. See Section14.6.4, for furthe r det ails about the register.
A sampling rate of 48kHz supports MPEG2 and MPE G4. A rate of 44.1kHz supports MP3.
14.5 Data Fo r mats
14.5.1 FIFO and Memory Format
FIFO buffers are 16 levels deep and 32 bits wide. T his stores 32 samples per channel in each
direction.
Audio data is stored with two samples (Left + Right) per 32-bit word, even if samples are smaller
than 16 bits. The Left channel data occupies bits [15:0], while the Right channel data uses bits
[31:16] of the 32-bit word. Within each 16-bit field, the audio sample is left-justified, with unused
bits packed as zeroes on the right-hand (LSB) side.
In memory, the mapping of stereo samples is the sa me as in the FIFO buffers. However, single-
channel audio occupies a full 32-bit word per sample, using either the upper or lower half of the
word, depending on whether it’s considered a Left or Right sample.
14.5.2 I2S and MSB-Justified Serial Audio Formats
I2S and MSB-Justified are similar protocols for digitized stereo audi o transmitted over a serial
path.
The BITCLK supplies the serial audio bit rate, the basis for the external CODEC bit-sampling
logic. Its frequency is 64 times the audi o sam pli ng fr eque ncy. Divided by 64, the resulting 8 k Hz to
48 kHz signal signifies timing for Left and Righ t serial data samples passing on the serial data
paths. This Left/Right signal is sent to the CODEC on the SYNC pin. Each phase of the Left/Right
signal is accompanied by one serial audio data sample on the data pins SDATA_IN and
SDATA_OUT.
Table 14-2. Supported Sampling Frequencies
Audio Clock
Divider
Register
(31:0)
SYSCLK =
147.6 MHz / (SADIV) BITCLK = SYSCLK / 4 SYNC or Sampling frequency = BITCLK / 64
0x0000_000C 12.288 MHz 3.072 MHz 48.000 kHz (closest std = 48 kHz)
0x0000_000D 11.343 MHz 2.836 MHz 44.308 kHz (closest std = 44.1 kHz)
0x0000_001A 5.671 MHz 1.418 MHz 22.154 kHz (closest std = 22.05 kHz)
0x0000_0024 4.096 MHz 1.024 MHz 16.000 kHz (closest std = 16.00 kHz)
0x0000_0034 2.836 MHz 708.92 kHz 11.077 kHz (closest std = 11.025 kHz)
0x0000_0048 2.048 MHz 512.00 kHz 8.000 kHz (closest std = 8.00 kHz)