Intel PXA255 3.4.3 GPIO Reset

3-8 Intel® PXA255 Processor Developer’s Manual

Clocks and Power Manager

Watchdog resets immediatel y revert to hardware resets when the nRESET pin is asserted.

Otherwise, the completion sequence for watchdog reset is:

1. The 3.6864MHz oscillator and internal PLL clock generators wait for stabilization. The

32.768kHz oscillator’s configuration and status are not affected by watchdog reset.

2. The nRESET_OUT pin is deasserted after tDHW_OUT. Refer to the Intel® PXA255 Processor

Electrical, Mechanical, and Thermal Specification.

3. The normal boot-up sequence begins. All processor units except the RTTR in the RTC and

parts of the Clocks and Power Manager return to their predefined reset conditions. Software

must examine the RCSR to determine the cause for the reboot.

3.4.3 GPIO Reset

A GPIO Reset is invoked when GP[1] is properly configured as a reset source and is asserted low

for greater than four 3.6864-MHz clock cycles. In GPIO Reset all processor units except the RTC,

parts of the Clocks and Power Manager, and the Memory Controller return to their predefined,

known states.

To use the GPIO Reset function, set it up through the GPIO Controller. The GP[1] pin must be

configured as an input and set to its alternate GPIO Reset function in the GPIO Controller. The

GPIO Reset alternate function is level-sensitive and not edge-triggered. To ensure no spurious

resets are generated when the alternate GPIO Reset function is set, follo w these steps:

1. GP[1] must be set up as an output with its data register set to a 1.

2. Externally drive the GP[1] pin to a high state.

3. Configure GP[1] as an input.

4. Configure GP[1] for its Alternate (R eset) Function.

The previous mode of operation does not affect a GPIO Reset. When performing a GPIO Reset,

nRESET_OUT is asserted. If GP[1] is asserted for less than four 3.6864-MHz clock cycles, the

processor may remain in its previous mode or enter into a GPIO reset.

GPIO Reset does not function in Sleep Mode because all GPIO pins’ Alternate Function Inputs are

disabled. External wake-up sources must be routed through one of the enabled GPIO wake-up

sources (see Section 3.5.3 for details) during Sleep Mode. GP[1] may be enabled as a wake-up

source.

During GPIO Reset, most, but not all, internal registers a nd p rocess es are h eld at th eir defin ed r eset

conditions. The exceptions are the RTC, the Clocks and Power Manager (unless otherwise noted),

and the Memory Controller. During GPIO Reset, the clocks un it continues to operate with its

previously programmed values, so the processor enters and exits GPIO Reset with the same clock

configurations. All pins except the oscillator and Memory Controller pins return to their reset

conditions and the nBATT_ FAULT and nVDD_FAULT pins are ignored.