Intel® PXA255 Processor Developer’s Manual 5-11
DMA Controller
•Internal Peripheral to Memory Transfers: Most peripherals do not send a request for trailing
bytes for on-chip peripheral to memory transfers. Refer to the appropriate section in this
document for details of a peripheral’ s opera tion . If the per ipher al sends out a reque st, the DM A
transfers the number of bytes equal to the smaller of DCMD[LENGTH] or DCMD[SIZE]. If
software must us programmed I/O to handle the trailing bytes, it must follow this sequence of
operation:
1.Writing a 0 to the DCSR[RUN] bit to stop the DMA channel.
2.Wait until the channel to stops.
3.Make reads to the channel’s registers to check the channel’s status.
4.Perform the programmed I/O transfers to the peripheral.
5. Set the DCSR[RUN] bit to a 1 and reset the DMA channel fo r future data tran sfers.
5.2 Transferring Data
The internal peripherals are connected to the DMAC via the peripheral bus and use flow-through
data transfers. The DMAC can also transfer data to and from any memory location with memory-
to-memory moves in flow-through transfer mode. External devices, such as companion chips, tha t
are directly connected to the external data pins must use flow-through data transfers.
Main memory includes any memory that the processor supports, except writes to flash. Writes to
flash are not supported and cause a bus error.
In flow-through transfer mode, data passes through the DMAC before it is latched by the
destination in its buffers/memor y. The DMAC can also perform memory-to -memory moves in
flow-through transfer mode.
5.2.1 Servicing Internal Peripherals
The DMAC provides the DMA Request to Channel Map Registers (DRCMRx) that contain four
bits used to assign a channel number for each poss ible DMA request. An internal peripheral can be
mapped to any of the 16 available channels. See Table 5-5 to configure the internal peripherals for
DMA accesses. Internal peripherals assert the request bit through the peripheral request bus
(PREQ). The signals from the PREQ are sampled on every peripheral clock (PCLK) and if any of
the PREQ signals are not zeroes, a lookup is performed on the corresponding bits of the DRCMRx.
This allows the request to be mapped to one of the channels.
If the internal peripheral address is in the DSADR, the DCMDx[FLOW SRC] b it must be s et t o a 1.
This allows the processor to wait for the request before it initiates the transfer. If the internal
peripheral address is in the DTADR, the DCMDx[FLOWTRG] bit must be set to a 1.
If DCMDx[IRQEN] is set to a 1, a DMA interrupt is requested at the end of the last cycle
associated with the byte that caused DCMDx[LENGTH] to decrement to 0.