Intel® PXA255 Processor Developer’s Manual ix
Contents
11.2 FICP Operation................................................................................................................11-1
11.2.1 4PPM Modulation...............................................................................................11-2
11.2.2 Frame Format.....................................................................................................11-3
11.2.3 Address Field......................................................................................................11-3
11.2.4 C ontr ol F ield......................................... ........................................... ... ................11-3
11.2.5 Data Field...........................................................................................................11-3
11.2.6 CRC Field...........................................................................................................11-4
11.2.7 Bau d Ra te Gen erat i on..................................................................... ...................11-4
11.2.8 R eceive Operation.............................................................. ................................11-4
11.2.9 Transmit Operation.............................................................................................11-5
11.2.10Transmit and Receive FIFOs..............................................................................11-6
11.2.11Trailing or Error Bytes in the Receive FIFO........................................................11-7
11.3 FICP Register Definitions................................................................................................11-7
11.3.1 FIC P Control Register 0 (ICCR0)........................................................................11-8
11.3.2 FIC P Control Register 1 (ICCR1)......................................................................11-10
11.3.3 FIC P Control Register 2 (ICCR2)......................................................................11-11
11.3.4 FICP Data Register (ICDR)...............................................................................11-12
11.3.5 FICP Status Register 0 (ICSR0).......................................................................11-13
11.3.6 FICP Status Register 1 (ICSR1).......................................................................11-15
11.4 FICP Register Summary................................................................................................11-16
12 USB Device Controller............................................................................ ....................................12-1
12.1 USB Overview.......................................................................... ... ....................................12-1
12.2 Device Configuration.......................................................................................................12-2
12.3 USB Protocol..................................................................... .......................................... ....12-2
12.3.1 Signalling Levels.................................................................................................12-3
12.3.2 Bit Encoding........................................................................................................12-3
12.3.3 Fie l d Form at s.................... ........................................... ... ....................................12-4
12.3.4 Packet Formats...................................................................................................12-5
12.3.5 Transaction Formats...........................................................................................12-6
12.3.6 UDC Device Requests........................................................................................12-8
12.3.7 Configuration......................................................................................................12-9
12.4 UDC Hardware Connection...........................................................................................12-10
12.4.1 Sel f- Po we red De vice.......................................................................... .... ..........12-10
12.4.2 Bus-Powered Devices........................................................................ .... ..........12-12
12.5 UDC Operation..............................................................................................................12-12
12.5.1 C ase 1: EP0 Con trol Read............................................. ..................................12-12
12.5.2 Case 2: EP0 Control Read with a Premature Status Stage..............................12-13
12.5.3 Case 3: EP0 Control Write With or Without a Premature Status
Stage................................................................................................................12-14
12.5.4 Case 4: EP0 No Data Command......................................................................12-15
12.5.5 C ase 5: EP1 Data Transmi t (BU L K-I N) . ........................................... .................12-15
12.5.6 Case 6: EP2 Data Receive (BULK-OUT)..........................................................12-16
12.5.7 C as e 7: EP3 Data Tran smit (I SOC HR ONOU S- IN)......... ..................................12-17
12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)........................................12-18
12.5.9 C as e 9: EP5 Data Tran smit (I NT ER RUPT - IN )....................................... ..........12-20
12.5.10Case 10: RESET Interrupt ................................................................................12-20
12.5.11Case 11: SUSPEND Interrupt...........................................................................12-21
12.5.12Case 12: RESUME Interrupt.............................................................................12-21
12.6 UDC Register Definitions...............................................................................................12-21