Intel PXA255 15.2.5 Error Detection, 15.2.6 Interrupts

15-8 Intel® PXA255 Processor Developer’s Manual

MultiMediaCard Controller

SPI mode is an optional secon da r y c om munication protocol. In SPI m od e , th e MM C MD and

MMDAT lines are unidirectional and only single block data tran sf ers are allowed. The MMCMD

signal is an output from the controller and sends the command token and write data to the MMC

card. The MMDAT signal is an input to the controller and receives the response token and read data

from the MMC card.

Note: When the card is in SPI mode, the only way to return to MMC mo de is b y t ogg ling t he p ower t o th e

card.

Card addressing is implemented with hardware chip se le c ts, MMCCS1 and MMCCS0. All

command, response, and data tokens are 8-bits long and are transmitted immediately following the

assertion of the respective chip select.

The command token is protected with a 7-bit CRC. The card always sends a response to a

command token. The response token has four form ats, inc luding a n 8-bit er ror re sponse. The length

of the response tokens is one, two, or five bytes.

SPI mode offers a non protected mode. In this mode, CRC bits of the comma nd, resp onse, and data

tokens are still required in the tokens but these bits are ignored by the card and the controller.

In write data transfers, the data is suffixed with an 8-bit CRC status token from the car d. As in

MMC mode, the card may indicate that it is busy by pulling the MMDAT line low after the status

token. In read data transfers, the card may respon d wit h th e data or a data err or token one by te lo ng.

15.2.5 Error Detection

The MMC controller detects these errors on the MMC bus and reports them in the status register

(MMC_STAT):

•Response CRC error: a CRC error was calculated on the command response.

•Response time out: the re sponse did not begin bef ore the specified number of clocks.

•Write data CRC error: the card returned a CRC status error on the data.

•Read data CRC error: a CRC error was calculated on the data.

•Read time out: the read data operation did not begin before the specified number of clocks.

•SPI data error: a read data error token was detected In SPI mode.

15.2.6 Interrupts

The MMC controller generates interrupts to sig nal the stat us of a command s equence. The sof twar e

is responsible for masking the interrupts appropriately, verifying the interrupts, and performing the

appropriate action as necessary.

Interrupts and masking are de sc ri b ed in Section15.5.11 and Section 15.5.12. The

CMDAT[DMA_EN] bit will a l so mask the MMC_I_MASK[RXFIFO_RD_REQ] a nd

MMC_I_MASK[TXFIFO_W R _R E Q ] interrupt bits.