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Intel S5000PSL, S5000XSL 3.2Enterprise South Bridge (ESB2-E), 3.1.4Snoop Filter (5000X MCH only)

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Intel® Server Boards S5000PSL and S5000XSL TPS

Design and Environmental Specifications

3.1.3.4.2.2Dual Branch Mode Sparing

Dual branch mode sparing requires that all eight DIMM sockets be populated and must comply with the following population rules.

DIMM_A1 and DIMM_B1 must be identical in organization, size and speed.

DIMM_A2 and DIMM_B2 must be identical in organization, size and speed.

DIMM_C1 and DIMM_D1 must be identical in organization, size and speed.

DIMM_C2 and DIMM_D2 must be identical in organization, size and speed.

DIMM_A1 and DIMM_A2 need not be identical in organization, size and speed.

DIMM_B1 and DIMM_B2 need not be identical in organization, size and speed.

DIMM_C1 and DIMM_C2 need not be identical in organization, size and speed.

DIMM_D1 and DIMM_D2 need not be identical in organization, size and speed.

Sparing should be enabled in BIOS setup.

The BIOS will configure Rank Sparing Mode.

The larger of the pairs {DIMM_A1, DIMM_B1}, {DIMM_A2, DIMM_B2},

{DIMM_C1, DIMM_D1}, and {DIMM_C2, DIMM_D2} are selected as the spare pair units.

3.1.4Snoop Filter (5000X MCH only)

The 5000X version of the MCH includes a snoop filter. Depending on the application of the server, this feature can be used to enhance the performance of the server by eliminating traffic on the snooped system bus of the processor being snooped. By removing snoops form the snooped bus, the full bandwidth is available for other transactions.

3.2Enterprise South Bridge (ESB2-E)

The ESB2-E is a multi-function device that provides four distinct functions: an I/O controller, a PCI-X* bridge, a GB Ethernet controller, and a baseboard management controller (BMC). Each function has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller.

The ESB2-E provides the gateway to all PC-compatible I/O devices and features. The server boards use the following ESB2-E features:

PCI-X bus interface

Six-channel SATA interface with SATA Busy LED Control

Dual GbE MAC

Baseboard Management Controller (BMC)

Single ATA interface, with Ultra DMA 100 capability

Universal Serial Bus 2.0 (USB) interface

Removable media drives

LPC bus interface

PC-compatible timer/counter and DMA controllers

APIC and 8259 interrupt controller

Power management

Revision 1.2	41
	Intel order number: D41763-003

Contents

Revision September Enterprise Platforms and Services Division – Marketing Revision History Disclaimers Table of ContentsIntel® Server Boards S5000PSL and S5000XSL TPS Table of Contents Intel® Server Boards S5000PSL and S5000XSL TPS Table of Contents Page Appendix C: POST Code Diagnostic LED Decoder List of Figures List of Tables List of Tables Page This page intentionally left blank 1.Introduction 1.1Chapter Outline 1.2Server Board Use Disclaimer Page 2.Server Board Overview 2.1Server Board Feature Set Page Page 2.2Server Board Layout 2.2.1Server Board Connector and Component Layout Figure 2. Major Board Components 2.2.2Server Board Mechanical Drawings Page Figure 5. Restricted Areas on Side Figure 6. Restricted Areas on Side Page Figure 8. CPU and Memory Duct Keepout 2.2.3Server Board ATX I/O Layout 3.Functional Architecture Page 3.1Intel® 5000P / 5000X Memory Controller Hub (MCH) 3.1.1System Bus Interface 3.1.2Processor Support 3.1.2.1Processor Population Rules 3.1.2.2Common Enabling Kit (CEK) Design Support Page 3.1.3Memory Sub-system 3.1.3.1Memory RASUM Features 3.1.3.2Supported Memory Note 3.1.3.3DIMM Population Rules and Supported DIMM Configurations Page Page 3.1.3.3.1Minimum Non-MirroredMode Configuration Grey 3.1.3.4Non-mirroredMode Memory Upgrades 3.1.3.4.1Mirrored Mode Memory Configuration 3.1.3.4.2Sparing Mode Memory Configuration Intel® 5000P/5000X Memory Controller Hub 3.1.4Snoop Filter (5000X MCH only) 3.2Enterprise South Bridge (ESB2-E) 3.2.1PCI Sub-system 3.2.1.1PCI32: 32-bit, 33-MHzPCI Sub-system 3.2.1.2PXA: 64-bit, 133-MHzPCI Sub-system 3.2.1.3PE0: One x4 PCI Express* Bus Segment 3.2.1.4PE1: One x4 PCI Express* Bus Segment 3.2.1.5PE2: One x4 PCI Express* Bus Segment 3.2.2Serial ATA Support 3.2.3Parallel ATA (PATA) Support 3.2.4USB 2.0 Support 3.3Video Support Page 3.3.1Video Modes 3.3.2Video Memory Interface 3.3.3Dual Video 3.4SAS Controller 3.4.1SAS RAID Support 3.4.2SAS / SATA Connector Sharing 3.5Network Interface Controller (NIC) 3.5.1Intel® I/O Acceleration Technolgy 3.6 Super I/O 3.6.1Serial Ports 3.6.2Floppy Disk Controller 3.6.3Keyboard and Mouse Support 3.6.4Wake-upControl 3.6.5System Health Support 4.Platform Management Page 5.Connector / Header Locations and Pin-outs 5.1Board Connector Information 5.2Power Connectors Table 12. 12 V Power Connector Pin-out(J3J2) Table 13. Power Supply Signal Connector Pin-out(J9D1) Table 14. P12V4 Power Connector Pin-out(J5A2) 5.3System Management Headers 5.3.1Intel® Remote Management Module (Intel® RMM) Connector 5.3.2LCP / AUX IPMB Header 5.3.3IPMB Header 5.3.4HSBP Header 5.3.5SGPIO Header 5.3.7HDD Activity LED Header 5.4Front Panel Connector 5.5I/O Connectors 5.5.1VGA Connector 5.5.2NIC Connectors 5.5.3IDE Connector 5.5.4Intel® Remote Management Module NIC Connector Page 5.5.5SATA / SAS Connectors 5.5.6Serial Port Connectors 5.5.7Keyboard and Mouse Connector 5.5.8USB Connector 5.6Fan Headers Page 6.Jumper Blocks 6.1CMOS Clear and Password Reset Usage Procedure 6.2BMC Force Update Procedure 6.3BIOS Select Jumper 7.Intel® Light Guided Diagnostics 7.15 Volt Standby LED 7.2Fan Fault LEDs 7.3System ID LED and System Status LED 7.3.1System Status LED – BMC Initialization Page 7.4DIMM Fault LEDs 7.5Processor Fault LEDs 7.6Post Code Diagnostic LEDs 8.Design and Environmental Specifications 8.1Server Boards S5000PSL and S5000XSL Design Specifications 8.2Server Board Power Requirements 8.2.1Processor Power Support 8.3.1Grounding 8.3.2Standby Outputs 8.3.3Remote Sense 8.3.4Voltage Regulation 8.3.5Dynamic Loading 8.3.6Capacitive Loading 8.3.7Ripple / Noise 8.3.8Timing Requirements Table 44. Output Voltage Timing Figure 25. Output Voltage Timing Table 45. Turn On/Off Timing Figure 26. Turn On/Off Timing (Power Supply Signals) 8.3.9Residual Voltage Immunity in Standby Mode 9.Regulatory and Certification Information 9.1 Product Regulatory Compliance 9.1.1Product Safety Compliance 9.1.2Product EMC Compliance – Class A Compliance 9.1.3Certifications / Registrations / Declarations 9.2Product Regulatory Compliance Markings 9.3 Electromagnetic Compatibility Notices 9.3.1FCC Verification Statement (USA) 9.3.2ICES-003(Canada) 9.3.3Europe (CE Declaration of Conformity) 9.3.4VCCI (Japan) 9.3.5BSMI (Taiwan) 9.3.6RRL (Korea) 9.3.7CNCA (CCC-China) 9.4Restriction of Hazardous Substances (RoHS) Compliance Appendix A: Integration and Usage Tips Appendix B: BMC Sensor Tables ƒRearm Sensors ƒDefault Hysteresis ƒCriticality ƒStandby Table 46. BMC Sensors Page Page Page Page Page Page Page Page Page Page Page Page Appendix C: POST Code Diagnostic LED Decoder Table 47. POST Progress Code LED Example Table 48. Diagnostic LED POST Code Decoder Page Page Page Appendix D: POST Code Errors Page POST Error Beep Codes Appendix E: Supported Intel® Server Chassis Glossary Page Page Reference Documents