Switch Management and Operating Concepts

STP Parameters for the Port Level

The following are the user-configurable STP parameters for the port or port group level.

Variable

Description

Default Value

 

 

 

 

Specifies the relative priority for each port. Lower

 

Port Priority

numbers specify a higher priority and a greater chance

128

 

of a given port being elected as the root port.

 

 

 

 

 

 

• 100 for 10 Mbps Fast

 

Specifies a value used by STP to evaluate paths. STP

Ethernet ports

 

• 19 for 100 Mbps Fast

Port Cost

calculates path costs and selects the path with the

Ethernet ports

 

minimum cost as the active path.

 

• 4 for 1000 Mbps Gigabit

 

 

 

 

Ethernet ports

 

 

 

Link Aggregation

The switch supports IEEE 802.3ad Link Aggregation which allows several ports to be grouped so that they can act as a single port. This is done to either increase the bandwidth of a network connection or to ensure fault recovery. The group has the following assignments:

•Master port-This port is the Ethernet port with the lowest port number. All member ports are configured to use its port settings and become members of its VLAN.

•Anchor port-This port is in charge of sending control packets, such as spanning tree BPDUs, and also the flooding of multicast frames. When a link change event occurs in the group, the anchor port may be re-elected.

The ZT 8101 supports up to six link aggregation groups, each of which may include from 2 - 8 switch ports. However, the gigabit ports (ports 25 and 26) cannot be included in a link aggregation group that contains 10/100 ports.

The switch supports both static link aggregation and dynamic link aggregation. Static link aggregation (Trunk mode) lets users define a fixed link aggregation path. Dynamic link aggregation uses Link Aggregation Control Protocol (LACP) which automatically detects the presence of other link aggregation devices in the network and lets them exchange data to configure and maintain link aggregation groups. The switch also supports LCAP Marker Protocol which provides for the controlled removal of aggregate link members and assures minimum or no loss of data when removing member links.

When a link aggregation group is deleted or disabled, the ports retain their reassigned port settings.

They do not recover their original port settings. For example, suppose that Port 1 belongs to

VLAN1 and Port 2 belongs to VLAN2. When you create a group with a starting point of Port 1 and a width of 2, Port 2 will be added to VLAN1 and removed from VLAN2 automatically. If you delete or disable the group later, the Port 2 will still be assigned to VLAN1.

When configuring Link Aggregation you can also specify the load sharing algorithm used. The default load sharing algorithm is Layer 3 IP Source Address. There are six load sharing algorithms to select from:

•Layer 2 MAC Source Address (SA)

Intel® NetStructure™ ZT 8101 10/100 Ethernet Switch User’s Manual

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Intel ZT 8101 10/100 user manual Link Aggregation, STP Parameters for the Port Level, Variable Description Default Value
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ZT 8101 10/100 specifications

The Intel ZT 8101 10/100 is a highly regarded network interface controller designed for efficient data communication in both home and enterprise environments. This versatile chip offers robust support for various networking technologies, making it suitable for a wide range of applications.

One of the most significant features of the Intel ZT 8101 is its capability to operate at both 10 Mbps and 100 Mbps, allowing for seamless integration into existing networks. This dual-speed functionality ensures that users can enjoy the benefits of faster data transfer rates while still maintaining compatibility with legacy hardware. The device automatically detects the network speed, facilitating a plug-and-play experience that minimizes user intervention.

The Intel ZT 8101 utilizes advanced features such as full-duplex support, which enables simultaneous data transmission and reception. This capability significantly enhances network efficiency and maximizes throughput, making it ideal for environments with high data traffic. Moreover, the chip employs sophisticated packet processing algorithms to prioritize data, reducing latency and ensuring smoother communication.

In terms of power efficiency, the Intel ZT 8101 is designed to consume minimal power, making it a suitable choice for energy-conscious applications. Its low power consumption allows for more efficient operations, contributing to overall system stability and longevity. Additionally, it incorporates power management features that can dynamically adjust the power usage based on network demand.

Another notable characteristic is the integration of hardware-based flow control, which helps prevent data packet loss during high-utilization periods. This capability is essential for maintaining the integrity of data transmission in busy network environments. The chip’s robust error detection and correction mechanisms further enhance data reliability, minimizing the chances of transmission errors.

The Intel ZT 8101 supports various network standards, including IEEE 802.3 and IEEE 802.3u, ensuring compatibility with a wide range of Ethernet devices. Its flexibility makes it an excellent choice for network upgrades, expansions, or new installations, allowing users to tailor their network infrastructure according to specific needs.

In summary, the Intel ZT 8101 10/100 network interface controller stands out for its dual-speed support, energy efficiency, and advanced networking features. Whether for home users looking to improve their network performance or businesses seeking reliable data communication solutions, the ZT 8101 represents a compelling choice that combines technology, reliability, and efficiency. As network demands continue to evolve, this Intel chip remains a fundamental component in many networking scenarios.
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