Motorola SSETM 5000 service manual Digital Signal Processor DSP, Baseband Interface Port BBP

Theory of Operation: VOCON Board 2-21

Digital Signal Processor (DSP)

The DSP portion of the dual-core processor performs signaling and voice encoding and decoding, as well as audio filtering and volume control. The DSP performs Private-Line/Digital Private-Line (PL/ DPL) encode and alert-tone generation. The DSP transmits pre-emphasis on analog signals, and applies a low-pass (splatter) filter to all transmitted signals. The DSP controls squelch, deviation, and executes receiver and transmitter filtering. The DSP executes a stored program located in the FLASH memory device.

The DSP requires a 16.8 MHz clock. The DSP uses the 16.8 MHz clock to generate a 256 kHz clock and an 8 kHz frame synchronization signal that is supplied to the CODEC. Additionally, the DSP requires clock and frame synchronization from the Abacus III digital back-end IC on the transceiver board to generate another clock and frame synchronization signal, and these signals are supplied to transmit DAC on the transceiver board.

The DSP has 84k x 24 bits of program RAM and 62k x 16 bits of data RAM. It has its own set of peripherals including the Baseband Interface Port (BBP), the DSP Timer module, and the Serial Audio CODEC Port (SAP). Additionally, the DSP shares some peripherals with the MCU, including the USB interface and the General Purpose Input/Output module (GPIO).

Baseband Interface Port (BBP)

The Baseband Interface Port (BBP) module is the DSP’s serial synchronous interface (SSI) to the transceiver board. The BBP has independent sections for the receiver and the transmitter. The receiver BBP pins include the receive data pin SRDB (U703 pin 4), the receive clock signal pin SC0B (U705 pin 4), and the receive frame synchronization (sync) signal pin SC1B (U704 pin 4). The transmitter's BBP pins include the transmit data pin STDB (R717), the transmit clock signal pin SCKB (R715), and the transmit frame sync signal pin SC2B (R711). All BBP lines use GPIO voltage logic levels.

DSP Timer Module

While the BBP receive clock and frame sync signals are supplied by the Abacus III IC from the transceiver board, the BBP transmit clock and frame sync signals are generated by the DSP Timer. The BBP receive clock, connected to the DSP Timer input pin T10, is reference used to generate the BBP transmit clock and frame sync signals. These two signals, along with the BBP transmit data signal, are connected to the DAC on the transceiver board.

Serial Audio CODEC Port (SAP)

The Serial Audio CODEC Port (SAP) module is the DSP’s serial synchronous interface (SSI) to the audio CODEC on the GCAP II IC. The SAP also interfaces with the encryption module.

The SAP interface consists of four signals including the SAP clock line pin SCKA (component R405), the SAP frame sync line pin SC2A (component R406), the SAP receive data line pin SRDA (component R402), and the transmit data line pin STDA (component R403).

The SAP clock is generated by the dual-core processor U401, and is a 256 kHz, 2.9 V peak-to-peak square wave. The SAP frame sync signal is generated by the dual-core processor U401, and is an 8 kHz, 2.9 V peak-to-peak square wave.

Universal Serial Bus (USB)

The dual-core processor USB peripheral, shared by the MCU and the DSP, provides the required buffering and protocol to communicate on the Universal Serial Bus. The dual-core processor supports USB slave functionality.

The receive data path is routed from the discrete USB receiver (U302 pin 8) and is buffered by U308. Single-ended positive data is generated at U302 pin 3 and is sent to the dual-core processor pin URXD_RTS.

6881094C12-A November 11, 2004