2-22 | Theory of Operation: VOCON Board |
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USB data minus comes from U302 pin 4 and this signal is sent to URXD1 of the dual-core processor.
General-Purpose Input/Output (GPIO) Module
The General-Purpose Input/Output (GPIO) module is shared by the MCU and the DSP. This module consists of four 16-pin bi-directional ports and a 15 pin bi-directional port. While some of the pins on these ports are being used for other functions (UART, SPI, SAP, BBP, and Interrupt pins), the remaining pins can be programmed to become GPIOs that can be used by either the DSP or the MCU. Each GPIO pin has up to 8 alternate output functions and up to 4 alternate input functions.
This allows for the GPIO pins to be routed internally to pertinent dual-core processor modules. Additionally, the GPIO module adds selectable edge-triggered or level-sensitive interrupt functionality to the GPIO pins. Some examples of GPIO pins include the Audio PA control signals (EXT_SPKR_SEL, AUDIO_PA_EN, and AUDIO_MODE_SEL), the EEPOT control signals (EEPOT_INC*, EEPOT_U_D*, EEPOT_CS*, and EEPOT_CS_EXT*), and the LED control signals (RED_LED and GREEN_LED).
System Clocks
Two main clocks are provided to the dual-core processor. The first clock, a 16.8 MHz sine wave, comes from the RF interface connector P201 pin 7. This is the most important clock, since it is used internally to generate the clocks for both the MCU and DSP cores, as well as most of the peripherals. It is conditioned by the clock buffer circuit, which includes Q601, R603, R605, R615, L601, C606, C609, R608, and C607. The output of this buffer (C452) goes to the dual-core processor CKIH pin, as well as to the digital-support IC REF_16_IN.
The other clock supplied to the dual-core processor is a 3 V peak-to-peak 32.768 kHz square wave (32 kHz test point). It is generated by the digital-support IC U301 internal oscillator and an external 32.768 kHz crystal Y301, and is supplied to the CKIL pin on the dual-core processor. While not as widely used as the 16.8 MHz clock, the 32.768 kHz clock is needed by some components in the dual-core processor, including the reset circuitry.
2.5.2.1.2 Static RAM (SRAM) U403
The static RAM (SRAM) IC U403 is an asynchronous, 1 MB, CMOS device that is capable of 70 ns access speed. It is supplied with 1.8 volts. The SRAM has its 19 address lines and 16 data lines connected to the EIM of the dual-core processor through the Address(23:0) and Data(15:0) busses.
The SRAM has an active-high chip select CS2 that is tied directly to the 1.8 V supply and an active low chip select CS1 that is connected to the EIM CS2_N pin (test point CS2). When the SRAM CS1 pin is not asserted, the SRAM is in standby mode, which reduces current consumption.
Two other control signals from the EIM that change the mode of the SRAM are the read/write signal, R/W, and the output enable signal, OE. The R/W of the EIM is connected to the SRAM EN_WE pin (test point R_W), while the OE signal from the EIM is connected to the SRAM EN_OE pin. The SRAM is in read mode when the EN_WE pin is not asserted and the EN_OE pin is asserted. The SRAM is in write mode when the EN_WE pin is asserted, regardless of the state of the EN_OE pin.
The other SRAM pins are the lower-byte enable pin LB and the upper-byte enable pin UB. These pins are used to determine which byte (LB controls data lines 0-7 and UB controls data lines 8-15) is being used when there is a read or a write request from the dual-core processor. The LB pin is controlled by the EIM EB1_N signal, while the UP pin is controlled by the EB0_N signal.
2.5.2.1.3 FLASH Memory U402
The Flash memory IC is an 8 MB CMOS device with simultaneous read/write or simultaneous read/ erase operation capabilities with 70 ns access speed. It is supplied with 1.8 volts. The Flash memory has its 22 address lines and 16 data lines connected to the EIM of the dual-core processor through
