Chapter4 HardwareOverview
NI5102 User Manual 4-8 ni.com
ADC Pipeline Delay
The ADC on the NI 5102 is a pipelined flash converter with a maximum
conversionrate of 20 MS/s. The pi pelined architecture imposes a 2.5 Scan
Clock cycle delay to convert analog voltage into a digital value, as shown
in Figure 4-7.
Figure 4-7. ScanClock Delay
Inreference to the Scan Clock signal, the digital value corresponding to the
firstconversion (the first falling edge of the Scan Clock signal) outputs
synchronously with the third rising edge of the Scan Clock signal.
Usinga pipelined architecture also introduces a lower limit on the scan rate.
Forthe NI 5102, the accuracy starts to degrade below about 1 kS/s.
The NI 5102 automatically adjusts for pipelined delay when you use the
internal scan clock. If you use an externalscan clock ,yo u must providea
free-running clock to ensure reliable operation. Youmust also follow
timing specificationson the external scan clock as described in
Appendix A, Specifications.
Acquisition Modes
The NI 5102 supports two acquisition modes—pretrigger acquisition and
posttrigger acquisition.
Posttrigger Acquisition
In posttrigger acquisition mode, the hardware acquires a number of scans
after the Start Trigger occurs. When the trigger occurs, the input signal is
digitized and the desired number of scans are stored in onboard memory.
Table 4-4 shows the minimum and maximum number of samples the
NI5 102 can acquire.
Input
ScanClock
1234
1234
56