3.0CONNECTING to the NEX-DDR3INTR-THIN INTERPOSER3.1General

Care should be taken to support the weight of the acquisition probes so that the Logic Analyzer Interposer board and/or target socket are not damaged.

3.2 B_DDR3D_2D Support

To acquire DDR3 Read and Write data at speeds up to 1066MT/s requires two merged TLA7BB4 136-channel, with 1.4G state option, acquisition cards and the use of the B_DDR3D_2D support software. The Master card will be in the lower numbered of the two cards. Slave card #1 is in the adjacent high-numbered slots. The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using (1) NEX-PPRB1X-T probes and three (3) NEX-PRB2X-T probes:

TLA Master

Connect the NEX-PRB1X-T “C” probe head to DDR3 Interposer’s LEASH (soldered-on coax cable) that is attached to “M_C” position on the Interposer.

Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “M_ A3/2 A1/0” position on the Interposer.

Match the label on the end of the NEX-PRB1X-T/2X-T probes with the labels on the front of the Tektronix Logic Analyzer Master module and connect.

TLA Slave

Connect the NEX-PRB2X-T A3/2 & A1/0 probe head to DDR3 Interposer’s LEASH that is attached to “S_ A3/2 A1/0” position on the Interposer.

Connect the NEX-PRB2X-T “C3/2” & “E3/2” probe head to DDR3 Interposer’s LEASH that is attached to “S_C3/2 E3/2” position on the Interposer.

See Figure 1 for connections. Table 1 shows the Channel Grouping / Wiring for use with the B_DDR3D_2D support.

3.3 B_DDR3D_2G Support

To acquire DDR3 Read and Write data from two or three DIMM slots, for total memory channel disassembly, at speeds up to 800MT/s requires two merged TLA7BB4 136-channel, with 1.4G state option, acquisition cards and the use of the B_DDR3D_2G optional support software. The Master card will be in the lower numbered, of the two cards. Slave card #1 will be in the adjacent high-numbered slots. This support requires an additional NEX-PRB1X-T (for a total of 2), and the NEX-PRBCOAX product. The logic analyzer modules should be connected to the DDR3 DIMM Interposer as follows using (1) NEX-PPRB1X-T probes and three (3) NEX- PRB2X-T probes, with the additional NEX-PRB1X-T connected to the NEX-PRBCOAX:

DDR3THIN-MN-XXX

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