Group | Signal | DDR3 | TLA | Group | Signal | DDR3 | TLA |
Name | Name | Pin # | Input | Name | Name | Pin # | Input |
WrB_DatHi | WR_B_DQ63 | 234 | S_D2:0^1 | WrB_DatLo | WR_B_DQ31 | 156 | M_D0:6^1 |
(Hex) | WR_B_DQ62 | 233 | S_D2:1^1 | (Hex) | WR_B_DQ30 | 155 | M_D0:3^1 |
| WR_B_DQ61 | 228 | S_D2:5^1 |
| WR_B_DQ29 | 150 | S_C0:0^1 |
| WR_B_DQ60 | 227 | S_Q1^1 |
| WR_B_DQ28 | 149 | S_C0:1^1 |
| WR_B_DQ59 | 115 | S_D2:2^1 |
| WR_B_DQ27 | 37 | M_D0:4^1 |
| WR_B_DQ58 | 114 | S_D2:3^1 |
| WR_B_DQ26 | 36 | M_D0:1^1 |
| WR_B_DQ57 | 109 | S_D2:7^1 |
| WR_B_DQ25 | 31 | S_C0:2^1 |
| WR_B_DQ56 | 108 | S_D3:0^1 |
| WR_B_DQ24 | 30 | S_C0:3^1 |
| WR_B_DQ55 | 225 | S_D3:2^1 |
| WR_B_DQ23 | 147 | S_C0:4^1 |
| WR_B_DQ54 | 224 | S_D3:3^1 |
| WR_B_DQ22 | 146 | S_C0:5^1 |
| WR_B_DQ53 | 219 | S_D3:7^1 |
| WR_B_DQ21 | 141 | S_C1:2^1 |
| WR_B_DQ52 | 218 | S_D1:5^1 |
| WR_B_DQ20 | 140 | S_C1:3^1 |
| WR_B_DQ51 | 106 | S_D3:1^1 |
| WR_B_DQ19 | 28 | S_C0:6^1 |
| WR_B_DQ50 | 105 | S_D3:4^1 |
| WR_B_DQ18 | 27 | S_C0:7^1 |
| WR_B_DQ49 | 100 | S_D1:7^1 |
| WR_B_DQ17 | 22 | S_C1:1^1 |
| WR_B_DQ48 | 99 | S_D1:6^1 |
| WR_B_DQ16 | 21 | S_C1:4^1 |
| WR_B_DQ47 | 216 | S_D1:4^1 |
| WR_B_DQ15 | 138 | S_C1:6^1 |
| WR_B_DQ46 | 215 | S_D1:1^1 |
| WR_B_DQ14 | 137 | S_C1:7^1 |
| WR_B_DQ45 | 210 | S_D0:7^1 |
| WR_B_DQ13 | 132 | S_E1:4^1 |
| WR_B_DQ44 | 209 | S_D0:6^1 |
| WR_B_DQ12 | 131 | S_E1:1^1 |
| WR_B_DQ43 | 97 | S_D1:3^1 |
| WR_B_DQ11 | 19 | S_C1:5^1 |
| WR_B_DQ42 | 96 | S_D1:2^1 |
| WR_B_DQ10 | 18 | S_E1:7^1 |
| WR_B_DQ41 | 91 | S_D0:5^1 |
| WR_B_DQ9 | 13 | S_E1:3^1 |
| WR_B_DQ40 | 90 | S_D0:4^1 |
| WR_B_DQ8 | 12 | S_E1:2^1 |
| WR_B_DQ39 | 207 | S_D0:3^1 |
| WR_B_DQ7 | 129 | S_E1:0^1 |
| WR_B_DQ38 | 206 | S_D0:2v |
| WR_B_DQ6 | 128 | S_E0:7^1 |
| WR_B_DQ37 | 201 | M_C0:1^1 |
| WR_B_DQ5 | 123 | S_E0:3^1 |
| WR_B_DQ36 | 200 | M_C0:4^1 |
| WR_B_DQ4 | 122 | S_E0:2^1 |
| WR_B_DQ35 | 88 | S_D0:1v |
| WR_B_DQ3 | 10 | S_CK2^1 |
| WR_B_DQ34 | 87 | S_D0:0^1 |
| WR_B_DQ2 | 9 | S_E0:5^1 |
| WR_B_DQ32 | 83 | M_C0:6^1 |
| WR_B_DQ1 | 4 | S_E0:1^1 |
| WR_B_DQ33 | 81 | M_C0:7^1 |
| WR_B_DQ0 | 3 | S_E0:0^1 |
Table 2 – B_DDR3D_2G (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.)
Notes:
1.All signals on this page are required for accurate
2.The ‘S’ in front of a TLA channel denotes the Slave card of the merged set
3.All signals on this page are stored in the TLA7BB4’s Prime memory and will not have a MagniVu display value
28 | Doc. Rev. 1.11 |