Nexus 21 1066MT/s Interposer, DDR3 800, NEX DDR3INTR THIN 35

Group	Signal	DDR3	TLA	Group	Signal	DDR3	TLA
Name	Name	Pin #	Input	Name	Name	Pin #	Input
WrA_DatHi	WR_A_DQ63	234	S_D2:0	WrA_DatLo	WR_A_DQ31	156	M_D0:6
(Hex)	WR_A_DQ62	233	S_D2:1	(Hex)	WR_A_DQ30	155	M_D0:3
	WR_A_DQ61	228	S_D2:5		WR_A_DQ29	150	S_C0:0
	WR_A_DQ60	227	S_Q1		WR_A_DQ28	149	S_C0:1
	WR_A_DQ59	115	S_D2:2		WR_A_DQ27	37	M_D0:4
	WR_A_DQ58	114	S_D2:3		WR_A_DQ26	36	M_D0:1
	WR_A_DQ57	109	S_D2:7		WR_A_DQ25	31	S_C0:2
	WR_A_DQ56	108	S_D3:0		WR_A_DQ24	30	S_C0:3
	WR_A_DQ55	225	S_D3:2		WR_A_DQ23	147	S_C0:4
	WR_A_DQ54	224	S_D3:3		WR_A_DQ22	146	S_C0:5
	WR_A_DQ53	219	S_D3:7		WR_A_DQ21	141	S_C1:2
	WR_A_DQ52	218	S_D1:5		WR_A_DQ20	140	S_C1:3
	WR_A_DQ51	106	S_D3:1		WR_A_DQ19	28	S_C0:6
	WR_A_DQ50	105	S_D3:4		WR_A_DQ18	27	S_C0:7
	WR_A_DQ49	100	S_D1:7		WR_A_DQ17	22	S_C1:1
	WR_A_DQ48	99	S_D1:6		WR_A_DQ16	21	S_C1:4
	WR_A_DQ47	216	S_D1:4		WR_A_DQ15	138	S_C1:6
	WR_A_DQ46	215	S_D1:1		WR_A_DQ14	137	S_C1:7
	WR_A_DQ45	210	S_D0:7		WR_A_DQ13	132	S_E1:4
	WR_A_DQ44	209	S_D0:6		WR_A_DQ12	131	S_E1:1
	WR_A_DQ43	97	S_D1:3		WR_A_DQ11	19	S_C1:5
	WR_A_DQ42	96	S_D1:2		WR_A_DQ10	18	S_E1:7
	WR_A_DQ41	91	S_D0:5		WR_A_DQ9	13	S_E1:3
	WR_A_DQ40	90	S_D0:4		WR_A_DQ8	12	S_E1:2
	WR_A_DQ39	207	S_D0:3		WR_A_DQ7	129	S_E1:0
	WR_A_DQ38	206	S_D0:2		WR_A_DQ6	128	S_E0:7
	WR_A_DQ37	201	M_C0:1		WR_A_DQ5	123	S_E0:3
	WR_A_DQ36	200	M_C0:4		WR_A_DQ4	122	S_E0:2
	WR_A_DQ35	88	S_D0:1		WR_A_DQ3	10	S_CK2
	WR_A_DQ34	87	S_D0:0		WR_A_DQ2	9	S_E0:5
	WR_A_DQ33	83	M_C0:6		WR_A_DQ1	4	S_E0:1
	WR_A_DQ32	81	M_C0:7		WR_A_DQ0	3	S_E0:0

Table 3 – B_DDR3D_3A (<=1066MT/s Read and Write) TLA Channel Grouping (cont’d.)

Notes:

1.All signals on this page are required for accurate post-processing of acquired data

2.The ‘M’ in front of a TLA channel denotes the Master card of the merged set

3.The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set

DDR3THIN-MN-XXX

35

Doc. Rev. 1.11

Contents

Page Limitation of Warranty Exclusive Remedies Software License Agreement License Agreement TABLE OF CONTENTS Page TABLE OF FIGURES TABLE OF TABLES Page 1.0OVERVIEW 1.1General Information 1.2 Software Package description B_DDR3D_2D Optional NEX-DDR3INTR-THIN 1.3 Eye size required 2.0 SOFTWARE INSTALLATION Okay 3.0CONNECTING to the NEX-DDR3INTR-THININTERPOSER 3.1General 3.2 B_DDR3D_2D Support TLA Master TLA Slave 3.4 B_DDR3D_3A Support two three TLA Slave1 TLA Slave2 3.5 Short “LEASH” probes 3.5.1 Samtec connector on the LEASH probe pins 3.5.2 LEASH probe to NEX-PRB1X/2Xconnection 3.5.3 Alternate use of NEX-PRB1Xor NEX-PRB2Xprobes 3.6 Slot Numbering Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.7 Display Groups not in Tables 1,2 or 4.0CLOCK SELECTION 4.1B_DDR3D_2D Clocking Selections SDRAM Clocking: S0#; Every Rising Edge S0# & S1#; Every Rising Edge Refresh Cycles: Acquire Do Not Acquire NOTE: 4.2 B_DDR3D_2G Clocking Selections C:____B:_0__A:___0 0r1r1r – C:____B:_0__A:__10 0r1r2r – C:____B:10__A:___0 4.3 B_DDR3D_3A Clocking Selections SDRAM DDR CLK0 Clocking: 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION 5.1 A Note About the Different Data Groups 5.2 MagniVu Signals Page Page Page Page Page Page Page Page 5.3 Adjusting Input Thresholds for Proper Data Acquisition 5.4 DDR3 and DDR3SPA 5.5 Selecting B_DDR3E_XX Read Data Sample Points 5.6 Selecting B_DDR3D_XX Write Data Sample Points NOTE 5.7 B_DDR3D_XX Support Setup Page Page Page Page Page Page 5.8 Setting B_DDR3D_3A Read Data Sample Points 6.0VIEWING DATA 6.1Viewing B_DDR3D_XX Data Burst Length CAS Latency (CL) CAS Additive Latency CAS Write Latency Registered DM Signal Use Show Hardware Software Control Flow 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports 6.3 B_DDR3D_2A / 3A Mnemonics Description Mnemonic Description 6.4 B_DDR3D_2G Mnemonics Description 6.5 Viewing Timing Data on the TLA Window New Data Window Waveform Window Type Page 7.0HINTS & TIPS 7.1Symbolic Triggering on a Command using B_DDR3D_XX Supports Symbol Definition 7.3 Capturing MRS (Mode Register Set) Cycles 7.4 Clock Capture quality 7.5 Thresholds APPENDIX A – How DDR Data is Clocked A.1 Background and A.2 DDR Acquisition - General A.3 B_DDR3D_2D / 2G / 3A Data Acquisition Write Wa Wb Wc Wd We APPENDIX B - Considerations B.1 NEX-DDR3INTR-THINBus Loading B.2 DIMM connector location for best quality signal capture B.3 TLA7BB4 Module to module skew APPENDIX C – 240-pinDDR3 DIMM Pinout APPENDIX C - 240-pinDDR3 DIMM Pinout (cont’d.) APPENDIX D –DataFlow Through the Probes (coax cable to channel) APPENDIX D - Data Flow Through the Probes (cont’d.) APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals Page APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bitData Group 8-bitData Group Strobe Data Bits Page APPENDIX J – Keep out area APPENDIX K – Simulation Model APPENDIX L - References APPENDIX M - Support About Nexus Technology, Inc Web site: http://www.nexustechnology.com Support Contact Information Technical Support techsupport@nexustechnology.com