Nexus 21 1066MT/s Interposer, DDR3 800, NEX DDR3INTR THIN 38

Group	Signal	DDR3	TLA
Name	Name	Pin #	Input
Control 2	CKE1	169	M_A3:2
(SYM)	CKE0	50	M_A3:1
	S3#	49	S2_C2:5
	S2#	48	S2_C3:0
	S1#	76	M_C3:4
	S0#	193	M_C3:3
	BA2	52	M_A3:0
	BA1	190	M_C3:7
	BA0	71	M_C1:6
	A15	171	M_CK0
	A14	172	M_A2:5
	A13	196	M_CK3
	A12/BC#	174	M_A2:4
	A10/AP	70	M_C1:3
	RAS#	192	M_C3:6
	CAS#	74	M_C3:5
	WE#	73	M_C1:7
Strobes	DQS7	111	S_A2:6
(HEX)	DQS6	103	S_A3:5
	DQS5	94	S_CK1
	DQS4	85	M_C2:3
	DQS3	34	M_A0:1
	DQS2	25	S_C3:0
	DQS1	16	S_E3:6
	DQS0	7	S_E2:4
Unprobed	All DQSx#
	DDRCK1+/-	63/64
	SA1	237
	SDA	238
	SA0	117
	SCL	118

Group	Signal	DDR3	TLA
Name	Name	Pin #	Input
Address 2	BA2	52	M_A3:0
(Hex)	BA1	190	M_C3:7
	BA0	71	M_C1:6
	A15	171	M_CK0
	A14	172	M_A2:5
	A13	196	M_CK3
	A12/BC#	174	M_A2:4
	A11	55	M_A2:6
	A10/AP	70	M_C1:3
	A9	175	M_A2:1
	A8	177	M_A2:0
	A7	56	M_A2:3
	A6	178	M_C0:3
	A5	58	M_A2:2
	A4	59	M_C0:5
	A3	180	M_C1:0
	A2	61	M_Q1
	A1	181	M_C1:1
	A0	188	M_C1:5
Misc 2	MISC1	Placeholder	M_A3:5
(OFF)	MISC0	Placeholder	M_A3:4
	DDRCK0+/- 184/185 M_C1:4
Ungrouped	DQS8	43	M_A1:2
	DM8	161	M_A1:1
	ERR_OUT#³	53	M_A2:7
	RESET#	168	M_A3:6
	TEST	167	M_A3:7
	ODT0	195	M_C2:0
	ODT1	77	M_C2:1
	PAR_IN	68	M_C1:2

Table 3 – B_DDR3D_3A TLA Channel Grouping (cont’d.)

Notes:

1.‘ # ‘ denotes a low-true signal

2.These signals are required for accurate acquisition and post-processing of acquired data

3.The ‘M’ in front of a TLA channel denotes the Master card of the merged set

4.The ‘S’ in front of a TLA channel denotes Slave card #1 of the merged set

5.The ‘S2’ in front of a TLA channel denotes Slave card #2 of the merged set

6.Signals in these groups are acquired using the TLA’s demux capability and will not have a MagniVu display value

DDR3THIN-MN-XXX

38

Doc. Rev. 1.11

Contents

Page Limitation of Warranty Exclusive Remedies Software License Agreement License Agreement TABLE OF CONTENTS Page TABLE OF FIGURES TABLE OF TABLES Page 1.0OVERVIEW 1.1General Information 1.2 Software Package description B_DDR3D_2D Optional NEX-DDR3INTR-THIN 1.3 Eye size required 2.0 SOFTWARE INSTALLATION Okay 3.0CONNECTING to the NEX-DDR3INTR-THININTERPOSER 3.1General 3.2 B_DDR3D_2D Support TLA Master TLA Slave 3.4 B_DDR3D_3A Support two three TLA Slave1 TLA Slave2 3.5 Short “LEASH” probes 3.5.1 Samtec connector on the LEASH probe pins 3.5.2 LEASH probe to NEX-PRB1X/2Xconnection 3.5.3 Alternate use of NEX-PRB1Xor NEX-PRB2Xprobes 3.6 Slot Numbering Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.7 Display Groups not in Tables 1,2 or 4.0CLOCK SELECTION 4.1B_DDR3D_2D Clocking Selections SDRAM Clocking: S0#; Every Rising Edge S0# & S1#; Every Rising Edge Refresh Cycles: Acquire Do Not Acquire NOTE: 4.2 B_DDR3D_2G Clocking Selections C:____B:_0__A:___0 0r1r1r – C:____B:_0__A:__10 0r1r2r – C:____B:10__A:___0 4.3 B_DDR3D_3A Clocking Selections SDRAM DDR CLK0 Clocking: 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION 5.1 A Note About the Different Data Groups 5.2 MagniVu Signals Page Page Page Page Page Page Page Page 5.3 Adjusting Input Thresholds for Proper Data Acquisition 5.4 DDR3 and DDR3SPA 5.5 Selecting B_DDR3E_XX Read Data Sample Points 5.6 Selecting B_DDR3D_XX Write Data Sample Points NOTE 5.7 B_DDR3D_XX Support Setup Page Page Page Page Page Page 5.8 Setting B_DDR3D_3A Read Data Sample Points 6.0VIEWING DATA 6.1Viewing B_DDR3D_XX Data Burst Length CAS Latency (CL) CAS Additive Latency CAS Write Latency Registered DM Signal Use Show Hardware Software Control Flow 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports 6.3 B_DDR3D_2A / 3A Mnemonics Description Mnemonic Description 6.4 B_DDR3D_2G Mnemonics Description 6.5 Viewing Timing Data on the TLA Window New Data Window Waveform Window Type Page 7.0HINTS & TIPS 7.1Symbolic Triggering on a Command using B_DDR3D_XX Supports Symbol Definition 7.3 Capturing MRS (Mode Register Set) Cycles 7.4 Clock Capture quality 7.5 Thresholds APPENDIX A – How DDR Data is Clocked A.1 Background and A.2 DDR Acquisition - General A.3 B_DDR3D_2D / 2G / 3A Data Acquisition Write Wa Wb Wc Wd We APPENDIX B - Considerations B.1 NEX-DDR3INTR-THINBus Loading B.2 DIMM connector location for best quality signal capture B.3 TLA7BB4 Module to module skew APPENDIX C – 240-pinDDR3 DIMM Pinout APPENDIX C - 240-pinDDR3 DIMM Pinout (cont’d.) APPENDIX D –DataFlow Through the Probes (coax cable to channel) APPENDIX D - Data Flow Through the Probes (cont’d.) APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals Page APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bitData Group 8-bitData Group Strobe Data Bits Page APPENDIX J – Keep out area APPENDIX K – Simulation Model APPENDIX L - References APPENDIX M - Support About Nexus Technology, Inc Web site: http://www.nexustechnology.com Support Contact Information Technical Support techsupport@nexustechnology.com