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Nexus 21 1066MT/s Interposer, DDR3 800, NEX DDR3INTR THIN APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.)

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APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.)

Samtec	Coax	TLA	DDR	Samte	Coax	TLA	DDR
Pin	Pin	Channe	3	c	Pin	Channe	3
		l	Signa	Pin		l	Signa
			l				l
15	J15-6	CK2+	DQS5	15	J15-6	Q2+	DQ3
29	J15-10	D1:7	DQ49	29	J15-10	E1:7	DQ10
25	J15-9	D1:6	DQ48	25	J15-9	E1:6	DQS1
28	J16-11	D1:5	DQ52	28	J16-11	E1:5	DM1
24	J16-12	D1:4	DQ47	24	J16-12	E1:4	DQ13
21	J15-8	D1:3	DQ43	21	J15-8	E1:3	DQ9
19	J15-7	D1:2	DQ42	19	J15-7	E1:2	DQ8
20	J16-13	D1:1	DQ46	20	J16-13	E1:1	DQ12
16	J16-14	D1:0	DM5	16	J16-14	E1:0	DQ7
12	J16-15	D0:7	DQ45	12	J16-15	E0:7	DQ6
10	J16-16	D0:6	DQ44	10	J16-16	E0:6	DM0
11	J15-5	D0:5	DQ41	11	J15-5	E0:5	DQ2
9	J15-4	D0:4	DQ40	9	J15-4	E0:4	DQS0
6	J16-17	D0:3	DQ39	6	J16-17	E0:3	DQ5
4	J16-18	D0:2	DQ38	4	J16-18	E0:2	DQ4
5	J15-3	D0:1	DQ35	5	J15-3	E0:1	DQ1
3	J15-2	D0:0	DQ34	3	J15-2	E0:0	DQ0
46	J16-6	CK1+	DQ60	46	J16-6	Q3+	DM2
32	J16-10	A1:7	DQ53	32	J16-10	E3:7	DQ14
36	J16-9	A1:6	DM6	36	J16-9	E3:6	DQ15
33	J15-11	A1:5	DQS6	33	J15-11	E3:5	DQ11
37	J15-12	A1:4	DQ50	37	J15-12	E3:4	DQ16
40	J16-8	A1:3	DQ54	40	J16-8	E3:3	DQ20
42	J16-7	A1:2	DQ55	42	J16-7	E3:2	DQ21
41	J15-13	A1:1	DQ51	41	J15-13	E3:1	DQ17
45	J15-14	A1:0	DQ56	45	J15-14	E3:0	DQS2
49	J15-15	A0:7	DQ57	49	J15-15	E2:7	DQ18
51	J15-16	A0:6	DQS7	51	J15-16	E2:6	DQ19
50	J16-5	A0:5	DQ61	50	J16-5	E2:5	DQ22
52	J16-4	A0:4	DM7	52	J16-4	E2:4	DQ23
55	J15-17	A0:3	DQ58	55	J15-17	E2:3	DQ24
57	J15-18	A0:2	DQ59	57	J15-18	E2:2	DQ25
56	J16-3	A0:1	DQ62	56	J16-3	E2:1	DQ28
58	J16-2	A0:0	DQ63	58	J16-2	E2:0	DQ29

2X Probe Connection used with	2X Probe Connection used with
B_DDR3D_2D software	B_DDR3D_2D software
S_A3/2 A1/0	S_C3/2 E3/2
(S2_A1/0 D1/0 Logic Analyzer Probe)	(S2_E3/2/1/0 Logic Analyzer Probe)

DDR3THIN-MN-XXX

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Doc. Rev. 1.11

Contents

Page Limitation of Warranty Exclusive Remedies Software License Agreement License Agreement TABLE OF CONTENTS Page TABLE OF FIGURES TABLE OF TABLES Page 1.0OVERVIEW 1.1General Information 1.2 Software Package description B_DDR3D_2D Optional NEX-DDR3INTR-THIN 1.3 Eye size required 2.0 SOFTWARE INSTALLATION Okay 3.0CONNECTING to the NEX-DDR3INTR-THININTERPOSER 3.1General 3.2 B_DDR3D_2D Support TLA Master TLA Slave 3.4 B_DDR3D_3A Support two three TLA Slave1 TLA Slave2 3.5 Short “LEASH” probes 3.5.1 Samtec connector on the LEASH probe pins 3.5.2 LEASH probe to NEX-PRB1X/2Xconnection 3.5.3 Alternate use of NEX-PRB1Xor NEX-PRB2Xprobes 3.6 Slot Numbering Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.7 Display Groups not in Tables 1,2 or 4.0CLOCK SELECTION 4.1B_DDR3D_2D Clocking Selections SDRAM Clocking: S0#; Every Rising Edge S0# & S1#; Every Rising Edge Refresh Cycles: Acquire Do Not Acquire NOTE: 4.2 B_DDR3D_2G Clocking Selections C:____B:_0__A:___0 0r1r1r – C:____B:_0__A:__10 0r1r2r – C:____B:10__A:___0 4.3 B_DDR3D_3A Clocking Selections SDRAM DDR CLK0 Clocking: 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION 5.1 A Note About the Different Data Groups 5.2 MagniVu Signals Page Page Page Page Page Page Page Page 5.3 Adjusting Input Thresholds for Proper Data Acquisition 5.4 DDR3 and DDR3SPA 5.5 Selecting B_DDR3E_XX Read Data Sample Points 5.6 Selecting B_DDR3D_XX Write Data Sample Points NOTE 5.7 B_DDR3D_XX Support Setup Page Page Page Page Page Page 5.8 Setting B_DDR3D_3A Read Data Sample Points 6.0VIEWING DATA 6.1Viewing B_DDR3D_XX Data Burst Length CAS Latency (CL) CAS Additive Latency CAS Write Latency Registered DM Signal Use Show Hardware Software Control Flow 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports 6.3 B_DDR3D_2A / 3A Mnemonics Description Mnemonic Description 6.4 B_DDR3D_2G Mnemonics Description 6.5 Viewing Timing Data on the TLA Window New Data Window Waveform Window Type Page 7.0HINTS & TIPS 7.1Symbolic Triggering on a Command using B_DDR3D_XX Supports Symbol Definition 7.3 Capturing MRS (Mode Register Set) Cycles 7.4 Clock Capture quality 7.5 Thresholds APPENDIX A – How DDR Data is Clocked A.1 Background and A.2 DDR Acquisition - General A.3 B_DDR3D_2D / 2G / 3A Data Acquisition Write Wa Wb Wc Wd We APPENDIX B - Considerations B.1 NEX-DDR3INTR-THINBus Loading B.2 DIMM connector location for best quality signal capture B.3 TLA7BB4 Module to module skew APPENDIX C – 240-pinDDR3 DIMM Pinout APPENDIX C - 240-pinDDR3 DIMM Pinout (cont’d.) APPENDIX D –DataFlow Through the Probes (coax cable to channel) APPENDIX D - Data Flow Through the Probes (cont’d.) APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals Page APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bitData Group 8-bitData Group Strobe Data Bits Page APPENDIX J – Keep out area APPENDIX K – Simulation Model APPENDIX L - References APPENDIX M - Support About Nexus Technology, Inc Web site: http://www.nexustechnology.com Support Contact Information Technical Support techsupport@nexustechnology.com