TABLE OF FIGURES

 

Figure 1 – Drawing of Interposer with probes attached ...............................................................

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Figure 2 – Samtec connector on the LEASH probe......................................................................

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Figure 3 – LEASH probe to NEX-PRB1X/2X connection ..........................................................

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Figure 4 - Read Data Latency = CAS Latency + CAS Additive Latency + RDIMM (5+0+1) = 6

cycles) ...........................................................................................................................................

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Figure 5 - Write Data Latency = CAS Write Latency + RDIMM (5+1) = 6 cycles.....................

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Figure 6 - Locating Minimum Valid B_DDR3D_XX Read Data Window .................................

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Figure 7 - Measuring B_DDR3D_XX RdA_DatHi / Lo Read Data Setup & Hold.....................

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Figure 8 - Measuring B_DDR3D_XX RdB_DatHi / Lo Read Data Setup & Hold .....................

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Figure 9 - Setting B_DDR3D_XX RdA_DatHi / Lo and RdB_DatHi / Lo Sample Points .........

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Figure 10 - Locating Minimum Valid B_DDR3D_XX Write Data Window ..............................

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Figure 11 - Measuring B_DDR3D_XX WrA_DatHi / Lo Write Data Setup & Hold..................

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Figure 12 - Measuring B_DDR3D_XX WrB_DatHi / Lo Write Data Setup & Hold..................

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Figure 13 - Setting B_DDR3D_XX WrA_DatHi / Lo and WrB_DatHi / Lo Sample Points ......

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Figure 14 - Viewing Individual 8-bit Read Data Groups .............................................................

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Figure 15 - Setting Individual Setup & Hold Values for the 8-bit Read Data Groups.................

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Figure 16 - B_DDR3D_XX Listing Display ................................................................................

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Figure 17 - Disassembly Properties ..............................................................................................

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Figure 18 - B_DDR3D_XX Listing Display - Control Flow .......................................................

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Figure 19 - B_DDR3D_XX MagniVu Display on TLA ..............................................................

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Figure 20 - B_DDR3D_2D MRS Trigger ....................................................................................

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Figure 21 - MRS Cycle Acquisition Disassembly........................................................................

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DDR3THIN-MN-XXX

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Doc. Rev. 1.11