Manuals / Brands / Computer Equipment / Computer Hardware / Nexus 21 / Computer Equipment / Computer Hardware

Nexus 21 1066MT/s Interposer, DDR3 800, NEX DDR3INTR THIN APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot

1 91

Download 91 pages, 3.42 Mb

APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1

Samte	Coax	TLA	DDR3	Samte	Coax	TLA	DDR3
c Pin	Pin	Channe	Signal	c	Pin	Channe	Signal
		l		Pin		l
15	J15-6	Q0+	CB1	46	J16-6	CK3+	A13
29	J15-10	D3:7	NC	32	J16-10	C3:7	BA1
25	J15-9	D3:6	CB3	36	J16-9	C3:6	RAS#
28	J16-11	D3:5	CB7	33	J15-11	C3:5	CAS#
24	J16-12	D3:4	CB6	37	J15-12	C3:4	S1#
21	J15-8	D3:3	CB2	40	J16-8	C3:3	S0#
19	J15-7	D3:2	DQS8	42	J16-7	C3:2	ODT0
20	J16-13	D3:1	DM8	41	J15-13	C3:1	ODT1
16	J16-14	D3:0	CB5	45	J15-14	C3:0	S2#
12	J16-15	D2:7	CB4	49	J15-15	C2:7	DQ32
10	J16-16	D2:6	DQ31	51	J15-16	C2:6	DQ33
11	J15-5	D2:5	CB0	50	J16-5	C2:5	S3#
9	J15-4	D2:4	DQ27	52	J16-4	C2:4	DQ36
6	J16-17	D2:3	DQ30	55	J15-17	C2:3	DQS4
4	J16-18	D2:2	DM3	57	J15-18	C2:2	NC
5	J15-3	D2:1	DQ26	56	J16-3	C2:1	DQ37
3	J15-2	D2:0	DQS3	58	J16-2	C2:0	DM4
46	J16-6	CK0+	A15	15	J15-6	Q1+	A2
32	J16-10	A3:7	TEST	29	J15-10	C1:7	WE#
36	J16-9	A3:6	RESET#	25	J15-9	C1:6	BA0
33	J15-11	A3:5	NC	28	J16-11	C1:5	A0
37	J15-12	A3:4	NC	24	J16-12	C1:4	CK0
40	J16-8	A3:3	NC	21	J15-8	C1:3	A10
42	J16-7	A3:2	CKE1	19	J15-7	C1:2	PAR_IN
41	J15-13	A3:1	CKE0	20	J16-13	C1:1	A1
45	J15-14	A3:0	BA2	16	J16-14	C1:0	A3
			ERR_OUT
49	J15-15	A2:7	#	12	J16-15	C0:7	NC
51	J15-16	A2:6	A11	10	J16-16	C0:6	NC
50	J16-5	A2:5	A14	11	J15-5	C0:5	A4
52	J16-4	A2:4	A12	9	J15-4	C0:4	NC
55	J15-17	A2:3	A7	6	J16-17	C0:3	A6
57	J15-18	A2:2	A5	4	J16-18	C0:2	NC
56	J16-3	A2:1	A9	5	J15-3	C0:1	NC
58	J16-2	A2:0	A8	3	J15-2	C0:0	NC

2X Probe Connection used with	1X Probe Connection used with
B_DDR3D_2D software	B_DDR3D_2D software
M_A3/2 A1/0	M_C3/2 C1/0
(S2_A3/2 D3/2 Logic Analyzer Probe)	(S2_C3/2/1/0 Logic Analyzer Probe)

DDR3THIN-MN-XXX

84

Doc. Rev. 1.11

Contents

Page Limitation of Warranty Exclusive Remedies Software License Agreement License Agreement TABLE OF CONTENTS Page TABLE OF FIGURES TABLE OF TABLES Page 1.0OVERVIEW 1.1General Information 1.2 Software Package description B_DDR3D_2D Optional NEX-DDR3INTR-THIN 1.3 Eye size required 2.0 SOFTWARE INSTALLATION Okay 3.0CONNECTING to the NEX-DDR3INTR-THININTERPOSER 3.1General 3.2 B_DDR3D_2D Support TLA Master TLA Slave 3.4 B_DDR3D_3A Support two three TLA Slave1 TLA Slave2 3.5 Short “LEASH” probes 3.5.1 Samtec connector on the LEASH probe pins 3.5.2 LEASH probe to NEX-PRB1X/2Xconnection 3.5.3 Alternate use of NEX-PRB1Xor NEX-PRB2Xprobes 3.6 Slot Numbering Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.7 Display Groups not in Tables 1,2 or 4.0CLOCK SELECTION 4.1B_DDR3D_2D Clocking Selections SDRAM Clocking: S0#; Every Rising Edge S0# & S1#; Every Rising Edge Refresh Cycles: Acquire Do Not Acquire NOTE: 4.2 B_DDR3D_2G Clocking Selections C:____B:_0__A:___0 0r1r1r – C:____B:_0__A:__10 0r1r2r – C:____B:10__A:___0 4.3 B_DDR3D_3A Clocking Selections SDRAM DDR CLK0 Clocking: 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION 5.1 A Note About the Different Data Groups 5.2 MagniVu Signals Page Page Page Page Page Page Page Page 5.3 Adjusting Input Thresholds for Proper Data Acquisition 5.4 DDR3 and DDR3SPA 5.5 Selecting B_DDR3E_XX Read Data Sample Points 5.6 Selecting B_DDR3D_XX Write Data Sample Points NOTE 5.7 B_DDR3D_XX Support Setup Page Page Page Page Page Page 5.8 Setting B_DDR3D_3A Read Data Sample Points 6.0VIEWING DATA 6.1Viewing B_DDR3D_XX Data Burst Length CAS Latency (CL) CAS Additive Latency CAS Write Latency Registered DM Signal Use Show Hardware Software Control Flow 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports 6.3 B_DDR3D_2A / 3A Mnemonics Description Mnemonic Description 6.4 B_DDR3D_2G Mnemonics Description 6.5 Viewing Timing Data on the TLA Window New Data Window Waveform Window Type Page 7.0HINTS & TIPS 7.1Symbolic Triggering on a Command using B_DDR3D_XX Supports Symbol Definition 7.3 Capturing MRS (Mode Register Set) Cycles 7.4 Clock Capture quality 7.5 Thresholds APPENDIX A – How DDR Data is Clocked A.1 Background and A.2 DDR Acquisition - General A.3 B_DDR3D_2D / 2G / 3A Data Acquisition Write Wa Wb Wc Wd We APPENDIX B - Considerations B.1 NEX-DDR3INTR-THINBus Loading B.2 DIMM connector location for best quality signal capture B.3 TLA7BB4 Module to module skew APPENDIX C – 240-pinDDR3 DIMM Pinout APPENDIX C - 240-pinDDR3 DIMM Pinout (cont’d.) APPENDIX D –DataFlow Through the Probes (coax cable to channel) APPENDIX D - Data Flow Through the Probes (cont’d.) APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals Page APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bitData Group 8-bitData Group Strobe Data Bits Page APPENDIX J – Keep out area APPENDIX K – Simulation Model APPENDIX L - References APPENDIX M - Support About Nexus Technology, Inc Web site: http://www.nexustechnology.com Support Contact Information Technical Support techsupport@nexustechnology.com