Nexus 21 1066MT/s Interposer, DDR3 800, NEX DDR3INTR THIN 47

Group	Signal	TLA	Group	Signal	TLA
Name	Name	Input	Name	Name	Input
CheckBit	CB7	M_A1:5	DataMasks	DM7	S_A2:4
s	CB6	M_A1:4		DM6	S_A3:6
	CB6	M_A1:4		DM6	S_A3:6
	CB5	M_A1:0		DM5	S_A1:0
	CB4	M_A0:7		DM4	M_C2:0
	CB3	M_A1:6		DM3	M_A0:2
	CB2	M_A1:3		DM2	S_CK3
	CB1	M_CK1		DM1	S_E3:5
	CB0	M_A0:5		DM0	S_E2:6
Strobes 2	DQS8	M_A1:2	Address 2	BA2	M_A3:0
	DQS7	S_A2:6		BA1	M_C3:7
	DQS6	S_A3:5		BA0	M_C1:6
	DQS5	S_CK1		A15	M_CK0
	DQS4	M_C2:3		A14	M_A2:5
	DQS3	M_A0:0		A13	M_CK3
	DQS2	S_C3:0		A12/BC#	M_A2:4
	DQS1	S_E3:6		A11	M_A2:6
	DQS0	S_E2:4		A10/AP	M_C1:3
Control 2	CKE1	M_A3:2		A9	M_A2:1
	CKE0	M_A3:1		A8	M_A2:0
	S3#	M_C2:5		A7	M_A2:3
	S2#	M_C3:0		A6	M_C0:2
	S1#	M_C3:4		A5	M_A2:2
	S0#	M_C3:3		A4	M_C0:5
	BA2	M_A3:0		A3	M_C1:0
	BA1	M_C3:7		A2	M_Q1
	BA0	M_C1:6		A1	M_C1:1
	A15	M_CK0		A0	M_C1:5
	A14	M_A2:5	Orphans	PAR_IN	M_C1:2
	A13	M_CK3		ERR_OUT#	M_A2:7
	A12/BC#	M_A2:4		TEST	M_A3:7
	A10/AP	M_C1:3		RESET#	M_A3:6
	RAS#	M_C3:6		ODT1	M_C3:1
	CAS#	M_C3:5		ODT0	M_C3:2
	WE#	M_C1:7	Misc 2,5	MISC1	M_A3:5
				MISC0	M_A3:4
				DDRCK0	M_C1:4

Table 4 – B_DDR3D_2D/_2G (<=1333MT/s Read and Write) TLA Channel Grouping (cont’d.)

Notes:

1.‘ # ‘ denotes a low-true signal

2.These signals are required for accurate acquisition and post-processing of acquired data

3.The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair

4.The ‘M’ in front of a TLA channel denotes the Master card of the merged pair

5.MISC1 and MISC0 are placeholders only and will not have interesting data on them

DDR3THIN-MN-XXX

47

Doc. Rev. 1.11

Contents

Page Limitation of Warranty Exclusive Remedies Software License Agreement License Agreement TABLE OF CONTENTS Page TABLE OF FIGURES TABLE OF TABLES Page 1.0OVERVIEW 1.1General Information 1.2 Software Package description B_DDR3D_2D Optional NEX-DDR3INTR-THIN 1.3 Eye size required 2.0 SOFTWARE INSTALLATION Okay 3.0CONNECTING to the NEX-DDR3INTR-THININTERPOSER 3.1General 3.2 B_DDR3D_2D Support TLA Master TLA Slave 3.4 B_DDR3D_3A Support two three TLA Slave1 TLA Slave2 3.5 Short “LEASH” probes 3.5.1 Samtec connector on the LEASH probe pins 3.5.2 LEASH probe to NEX-PRB1X/2Xconnection 3.5.3 Alternate use of NEX-PRB1Xor NEX-PRB2Xprobes 3.6 Slot Numbering Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.7 Display Groups not in Tables 1,2 or 4.0CLOCK SELECTION 4.1B_DDR3D_2D Clocking Selections SDRAM Clocking: S0#; Every Rising Edge S0# & S1#; Every Rising Edge Refresh Cycles: Acquire Do Not Acquire NOTE: 4.2 B_DDR3D_2G Clocking Selections C:____B:_0__A:___0 0r1r1r – C:____B:_0__A:__10 0r1r2r – C:____B:10__A:___0 4.3 B_DDR3D_3A Clocking Selections SDRAM DDR CLK0 Clocking: 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION 5.1 A Note About the Different Data Groups 5.2 MagniVu Signals Page Page Page Page Page Page Page Page 5.3 Adjusting Input Thresholds for Proper Data Acquisition 5.4 DDR3 and DDR3SPA 5.5 Selecting B_DDR3E_XX Read Data Sample Points 5.6 Selecting B_DDR3D_XX Write Data Sample Points NOTE 5.7 B_DDR3D_XX Support Setup Page Page Page Page Page Page 5.8 Setting B_DDR3D_3A Read Data Sample Points 6.0VIEWING DATA 6.1Viewing B_DDR3D_XX Data Burst Length CAS Latency (CL) CAS Additive Latency CAS Write Latency Registered DM Signal Use Show Hardware Software Control Flow 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports 6.3 B_DDR3D_2A / 3A Mnemonics Description Mnemonic Description 6.4 B_DDR3D_2G Mnemonics Description 6.5 Viewing Timing Data on the TLA Window New Data Window Waveform Window Type Page 7.0HINTS & TIPS 7.1Symbolic Triggering on a Command using B_DDR3D_XX Supports Symbol Definition 7.3 Capturing MRS (Mode Register Set) Cycles 7.4 Clock Capture quality 7.5 Thresholds APPENDIX A – How DDR Data is Clocked A.1 Background and A.2 DDR Acquisition - General A.3 B_DDR3D_2D / 2G / 3A Data Acquisition Write Wa Wb Wc Wd We APPENDIX B - Considerations B.1 NEX-DDR3INTR-THINBus Loading B.2 DIMM connector location for best quality signal capture B.3 TLA7BB4 Module to module skew APPENDIX C – 240-pinDDR3 DIMM Pinout APPENDIX C - 240-pinDDR3 DIMM Pinout (cont’d.) APPENDIX D –DataFlow Through the Probes (coax cable to channel) APPENDIX D - Data Flow Through the Probes (cont’d.) APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals Page APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bitData Group 8-bitData Group Strobe Data Bits Page APPENDIX J – Keep out area APPENDIX K – Simulation Model APPENDIX L - References APPENDIX M - Support About Nexus Technology, Inc Web site: http://www.nexustechnology.com Support Contact Information Technical Support techsupport@nexustechnology.com