Table 7 gives a brief description of each of the text lines displayed in the B_DDR3D_2G postprocessing software display.
Mnemonic | Description |
ACT – BANK ACTIVATE | Active command – activate a row in a bank for subsequent access |
(Sx# / bS# / cS#) Bank: | (Slot A, B or C; Chip Select |
DESL - IGNORE COMMAND | Deselect function – no new command |
(E)MRS – (EXTENDED) MODE | Mode Register Set command, registers |
REGISTER SET x (Sx# / bS# / cS#) | (Slot A, B or C; Chip Select |
NOP - NO OPERATION (Sx# / bS# / cS#) | No Operation command (Slot A, B or C; Chip Select |
PRE – SINGLE BANK PRECHARGE | Precharge command (Slot A, B or C; Chip Select |
(Sx# / bS# / cS#) Bank: |
|
PREA – PRECHARGE ALL BANK | Precharge All command (Slot A, B or C; Chip Select |
(Sx# / bS# / cS#) |
|
RDA – READ W/AUTO PRECHARGE | Read command with auto precharge |
(Sx# / bS# / cS#) Bank: | (Slot A, B or C; Chip Select |
RD - READ (Sx# / bS# / cS#) Bank: | Read command – initiates a burst read access to active row |
| (Slot A, B or C; Chip Select |
READ DATA | Valid Read data on the bus |
REF - REFRESH (Sx# / bS# / cS#) | Self Refresh command (Slot A, B or C; Chip Select |
WRA – WRITE W/AUTO PRECHARGE | Write command with auto precharge |
(Sx# / bS# / cS#) Bank: | (Slot A, B or C; Chip Select |
WR - WRITE (Sx# / bS# / cS#) Bank: | Write command – initiates a burst write access to active row |
| (Slot A, B or C; Chip Select |
WRITE DATA | Valid Write data on the bus |
ZQCL – ZQ CALIBRATION LONG | ZQ Calibration Long (Slot A, B or C; Chip Select |
(Sx# / bS# / cS#) |
|
ZQCS – ZQ CALIBRATION SHORT | ZQ Calibration Short (Slot A, B or C; Chip Select |
(Sx# / bS# / cS#) |
|
Table 7 - B_DDR3D_2G Mnemonics Definition
6.5 Viewing Timing Data on the TLABy default, the TLA will display an acquisition in the Listing (State) mode. However, the same data can be displayed in Timing form by adding a Waveform Display window. This is done by clicking on the Window
67 | Doc. Rev. 1.11 |