A.3 B_DDR3D_2D / 2G / 3A Data AcquisitionThese supports requires two (2) merged 136-channel with 1.4G state option TLA7BB4 acquisition cards used in a TLA7XX logic analyzer. Data is acquired using the rising edge of the DDR clock. A_Data information is earlier (older) data than the information stored in B_Data. Different Sample Points must be set for each of the four 32-bit Data groups, and, if necessary, sample points can be set for any of the 8-bit data groups or for individual data bits.
Clock
RdA-S&H
RdB-S&H 
Write Wa Wb Wc Wd We
WrA-S&H
WrB-S&H
DDR3THIN-MN-XXX | 74 | Doc. Rev. 1.11 |