Nexus 21 1066MT/s Interposer, DDR3 800, NEX DDR3INTR THIN 49

Group	Signal	TLA	Group	Signal	TLA
Name	Name	Input	Name	Name	Input
DataByte	DQ63	S_A2:0	DataByte	DQ31	M_A0:6
7	DQ62	S_A2:1	3	DQ30	M_A0:3
	DQ62	S_A2:1		DQ30	M_A0:3
	DQ61	S_A2:5		DQ29	S_C2:0
	DQ60	S_CK0		DQ28	S_C2:1
	DQ59	S_A2:2		DQ27	M_A0:4
	DQ58	S_A2:3		DQ26	M_A0:1
	DQ57	S_A2:7		DQ25	S_C2:2
	DQ56	S_A3:0		DQ24	S_C2:3
DataByte	DQ55	S_A3:2	DataByte	DQ23	S_C2:4
6	DQ54	S_A3:3	2	DQ22	S_C2:5
	DQ54	S_A3:3		DQ22	S_C2:5
	DQ53	S_A3:7		DQ21	S_C3:2
	DQ52	S_A1:5		DQ20	S_C3:3
	DQ51	S_A3:1		DQ19	S_C2:6
	DQ50	S_A3:4		DQ18	S_C2:7
	DQ49	S_A1:7		DQ17	S_C3:1
	DQ48	S_A1:6		DQ16	S_C3:4
DataByte	DQ47	S_A1:4	DataByte	DQ15	S_C3:6
5	DQ46	S_A1:1	1	DQ14	S_C3:7
	DQ46	S_A1:1		DQ14	S_C3:7
	DQ45	S_A0:7		DQ13	S_E3:4
	DQ44	S_A0:6		DQ12	S_E3:1
	DQ43	S_A1:3		DQ11	S_C3:5
	DQ42	S_A1:2		DQ10	S_E3:7
	DQ41	S_A0:5		DQ9	S_E3:3
	DQ40	S_A0:4		DQ8	S_E3:2
DataByte	DQ39	S_A0:3	DataByte	DQ7	S_E3:0
4	DQ38	S_A0:2	0	DQ6	S_E2:7
	DQ38	S_A0:2		DQ6	S_E2:7
	DQ37	M_C2:1		DQ5	S_E2:3
	DQ36	M_C2:4		DQ4	S_E2:2
	DQ35	S_A0:1		DQ3	S_Q3
	DQ34	S_A0:0		DQ2	S_E2:5
	DQ33	M_C2:6		DQ1	S_E2:1
	DQ32	M_C2:7		DQ0	S_E2:0

Table 5 – B_DDR3D_3A TLA MagniVu Channel Grouping (cont’d.)

Notes:

1.The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair

2.The ‘M’ in front of a TLA channel denotes the Master card of the merged pair

DDR3THIN-MN-XXX

49

Doc. Rev. 1.11

Contents

Page Limitation of Warranty Exclusive Remedies Software License Agreement License Agreement TABLE OF CONTENTS Page TABLE OF FIGURES TABLE OF TABLES Page 1.0OVERVIEW 1.1General Information 1.2 Software Package description B_DDR3D_2D Optional NEX-DDR3INTR-THIN 1.3 Eye size required 2.0 SOFTWARE INSTALLATION Okay 3.0CONNECTING to the NEX-DDR3INTR-THININTERPOSER 3.1General 3.2 B_DDR3D_2D Support TLA Master TLA Slave 3.4 B_DDR3D_3A Support two three TLA Slave1 TLA Slave2 3.5 Short “LEASH” probes 3.5.1 Samtec connector on the LEASH probe pins 3.5.2 LEASH probe to NEX-PRB1X/2Xconnection 3.5.3 Alternate use of NEX-PRB1Xor NEX-PRB2Xprobes 3.6 Slot Numbering Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page 3.7 Display Groups not in Tables 1,2 or 4.0CLOCK SELECTION 4.1B_DDR3D_2D Clocking Selections SDRAM Clocking: S0#; Every Rising Edge S0# & S1#; Every Rising Edge Refresh Cycles: Acquire Do Not Acquire NOTE: 4.2 B_DDR3D_2G Clocking Selections C:____B:_0__A:___0 0r1r1r – C:____B:_0__A:__10 0r1r2r – C:____B:10__A:___0 4.3 B_DDR3D_3A Clocking Selections SDRAM DDR CLK0 Clocking: 5.0 CONFIGURING FOR READ / WRITE DATA ACQUISITION 5.1 A Note About the Different Data Groups 5.2 MagniVu Signals Page Page Page Page Page Page Page Page 5.3 Adjusting Input Thresholds for Proper Data Acquisition 5.4 DDR3 and DDR3SPA 5.5 Selecting B_DDR3E_XX Read Data Sample Points 5.6 Selecting B_DDR3D_XX Write Data Sample Points NOTE 5.7 B_DDR3D_XX Support Setup Page Page Page Page Page Page 5.8 Setting B_DDR3D_3A Read Data Sample Points 6.0VIEWING DATA 6.1Viewing B_DDR3D_XX Data Burst Length CAS Latency (CL) CAS Additive Latency CAS Write Latency Registered DM Signal Use Show Hardware Software Control Flow 6.2 Viewing Raw DDR3 Data using B_DDR3D_XX Supports 6.3 B_DDR3D_2A / 3A Mnemonics Description Mnemonic Description 6.4 B_DDR3D_2G Mnemonics Description 6.5 Viewing Timing Data on the TLA Window New Data Window Waveform Window Type Page 7.0HINTS & TIPS 7.1Symbolic Triggering on a Command using B_DDR3D_XX Supports Symbol Definition 7.3 Capturing MRS (Mode Register Set) Cycles 7.4 Clock Capture quality 7.5 Thresholds APPENDIX A – How DDR Data is Clocked A.1 Background and A.2 DDR Acquisition - General A.3 B_DDR3D_2D / 2G / 3A Data Acquisition Write Wa Wb Wc Wd We APPENDIX B - Considerations B.1 NEX-DDR3INTR-THINBus Loading B.2 DIMM connector location for best quality signal capture B.3 TLA7BB4 Module to module skew APPENDIX C – 240-pinDDR3 DIMM Pinout APPENDIX C - 240-pinDDR3 DIMM Pinout (cont’d.) APPENDIX D –DataFlow Through the Probes (coax cable to channel) APPENDIX D - Data Flow Through the Probes (cont’d.) APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot APPENDIX E – B_DDR3D_2D Support Pinout, DIMM Slot 0 (Cont’d.) APPENDIX F – B_DDR3_2G Support Pinout, DIMM Slot 0 Auxiliary Signals Page APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot APPENDIX G – B_DDR3D_3A Support Pinout, DIMM Slot 1 (cont’d.) APPENDIX H – Data Group / Data Byte / Strobe Cross-Reference 32-bitData Group 8-bitData Group Strobe Data Bits Page APPENDIX J – Keep out area APPENDIX K – Simulation Model APPENDIX L - References APPENDIX M - Support About Nexus Technology, Inc Web site: http://www.nexustechnology.com Support Contact Information Technical Support techsupport@nexustechnology.com