Page516 of 544 NTAK93D-channel handler interface
553-3011-100 Standard14.00 January 2002
Read Only Memory (ROM)
A total of 32K bytes of ROM space for each pair of ports is reserved as a code
section of the DCH-PORT firmware.
LAPD Data Link/Asynchronous Controller
One chip controls each pair of independent communication ports. It performs
the functions of serial-to-parallel and parallel-to-serial conversions, error
detection, frame recognition (in HDLC) function. The parameters of these
functions are supplied by the DCH-PORT firmware.
Counter/Timer controller
Two chips are used as real-time timers and baud-rate generators for each pair
of communication ports.
Software interface circuit
This portion of the circuit handles address/data bus multiplexing, the
interchange of data, commands, and status between the on board processors
and software. It includes transmit buffer, receive buffer, command register,
and status register for each communication channel.
DPNSS/DCHI Port
The mode of operation of the DCH-PORT is controlled by a switch setting on
the NTAK09/NTBK50. For DPNSS the switch is ON; for DCHI it is OFF.
The port will operate at :
The address of ports is selected by hardwired backplane card address.
Port characteristics and LAPD parameters are downloaded from
software.
Data Rate 56kbps, 64kbps
Duplex Full
Clock Internal / External
Interface RS422