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| Table | DTE Interface Signal Assignments (Cont.) |
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| V.35 |
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| X.21 |
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Signal |
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Function |
| Stand- | Frame | Standalone | Standalone | Frame | Standalone |
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| alone |
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| and Frame |
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| Pin Circuit/ |
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| Frame |
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| Pin Circuit | Pin Circuit |
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External |
| 24 | 19 | U SCTE(A) | 113 | 24 | DA(A) | 24 | 7 | (A)* | A serial data | |||
Transmit |
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| 16 | W SCTE(B) 113 | 11 | DA(B) | 11 | 14 | (B)* | rate clock input | ||||
Clock |
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| from the data | |
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| source. Positive | |
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| clock | |
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| transitions must | |
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| correspond to | |
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| data transitions. | |
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Transmit |
| 15 | 14 | Y | SCT(A) | 114 | 15 | DB(A) | 15 | 6 | S(A) | A transmit data | ||
Clock |
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| 10 | A | SCT(B) | 114 | 12 | DB(B) | 12 | 13 | S(B) | rate clock for | ||
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| [SIGNAL | use by an | |
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| TIMING] | external data | |
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| source. Positive | |
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| clock | |
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| transitions | |
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| correspond to | |
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| data | |
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Receive Clock |
| 17 | 22 | X | SCR(B) | 115 | 17 | DD(A) |
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| A receive data | ||
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| 23 | V SCR(A) | 115 | 9 | DD(B) |
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| clock output | |||
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| for use by | |
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| external data | |
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| sink. Positive | |
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| clock | |
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| transitions | |
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| correspond to | |
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| data | |
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| transitions. | |
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Local Analog |
| 18 | 18 | L and j | 141 | 18 | LL |
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Loop |
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| input; when | |
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| on, commands | |
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| Local Analog | |
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| Loopback | |
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| (V.54 Loop 3). | |
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| See Table | |
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| Note |
| * Unassigned pins according to X.21 standard. |
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General
Order from: Cutter Networks | www.bestdatasource.com |