SOYO SY-5S manual ROM PCI/ISA Bios Chipset Features Setup

BIOS Setup Utility SY-5STM

3-3 CHIPSET FEATURES SETUP

Caution: Change these settings only if you are already familiar with the Chipset.

The [CHIPSET FEATURES SETUP] option changes the values of the chipset registers. These registers control the system options in the computer.

	ROM PCI/ISA BIOS
	CHIPSET FEATURES SETUP
	AWARD SOFTWARE, INC.
Auto Configuration	: Enabled	CPU to PCI Burst Mem. WR			: Disabled
		ISA Bus Clock Frequency			: PCICLK/4
L2 (WB) Tag Bit Length	: 7bits	System BIOS Cacheable			: Enabled
SRAM Back-to-Back	: Enabled	Video BIOS Cacheable			: Enabled
NA# Enable	: Enabled	Memory Hole At 15M-16M			: Disabled
Starting Point of Paging	: 1T	VGA Shared Memory Size			: 1	MB
Refresh Cycle Time (us)	: 15.6	VGA Memory Clock (MHz)			: 55
RAS Pulse Width Refresh	: 6T	Linear Mode SRAM Support			: Disabled
RAS Precharge Time	: 3T
RAS to CAS Delay	: 3T
CAS# Pulse Width (FP)	: 2T
CAS# Pulse Width (EDO)	: 1T
RAMW# Assertion Timing	: 3T
CAS Precharge Time (FP)	: 1T/2T	ESC	: Quit			: Select Item
CAS Precharge Time (EDO)	: 1T/2T	F1	: Help	PU/PD/+/-		: Modify
SDRAM WR Retire Rate	: X-2-2-2	F5	: Old Values	(Shift) F2		: Color
SDRAN Wait State Control	: 1WS	F6	: Load BIOS Defaults
Enhanced Memory Write	: Disabled	F7	: Load Setup Defaults
Read Refresh Memory RD	: Enabled
CPU to PCI Post Write	: 4T

After you have completed the changes, press [Esc] and follow the instructions on your screen to save your settings or exit without saving.

The following table describes each field in the CHIPSET FEATURES SETUP Menu and how to configure each parameter.

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