SOYO SY-5S ISA Bus Clock Frequency System Bios Cacheable, VGA Shared, Memory Size, VGA Memory

BIOS Setup Utility			SY-5STM
CHIPSET FEATURES SETUP (Continued)
CHIPSET	Setting	Description		Note
FEATURES

ISA Bus Clock Frequency

System BIOS Cacheable

PCILK/4	The ISA bus runs on PCI	Default
	Bus Clock divided by 4.
PCILK/3	The ISA bus runs on PCI
	Bus Clock divided by 3.
7.159MHz	ISA bus clock fixed to	Read-
	7.159MHz when [Auto	Only
	Configuration] field is set to
	[Enabled].
Disabled
Enabled	The ROM area F0000H-	Default
	FFFFFH is cacheable.

Video BIOS

Cacheable

Memory Hole At 15M-16M

Disabled

Enabled The video BIOS C0000H- Default C7FFFH is cacheable.

Disabled Default

Enabled Some interface cards will map their ROM address to this area. If this occurs, select [Enabled] in this field.

VGA Shared
	1 MB	VGA memory size shared	Default
Memory Size	0.5-4 MB	with system memory.
VGA Memory
	40	Selects the frequency of the	Default
Clock (MHz)	40-70 MHz	VGA memory clock.
The following field applies to Cyrix type of CPUs only.
Linear Mode	Disabled		Default
SRAM Support	Enabled	Linear mode SRAM support
		for Cyrix type of CPU.

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