Texas Instruments warranty Application Information, MSP430x11x1 MIXED SIGNAL MICROCONTROLLER

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

APPLICATION INFORMATION

Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features

P1SEL.x		VCC
	0
P1DIR.x
		See Note 27
Direction Control	1
From Module	0	See Note 28
P1OUT.x		Pad Logic
	1	P1.4±P1.7
Module X OUT
		See Note 28

See Note 27

	GND
	TST
P1IN.x	Bus Keeper
	EN
Module X IN	D

TST

TEST

P1IRQ.x

P1IE.x

Interrupt

Fuse

60 kΩ

EN

Q

Edge

Typical

P1IFG.x

Set

Select

GND

Fuse

Interrupt

P1IES.x

Control By JTAG

Flag

Blow

NOTE: Fuse not implemented

P1SEL.x

Control

in F11x1

P1.x

TDO

Controlled By JTAG

P1.7/TDI/TDO

Controlled by JTAG

TDI

TST

P1.x

P1.6/TDI

NOTE: The test pin should be protected from potential EMI

TST

P1.x

and ESD voltage spikes. This may require a smaller

TMS

external pulldown resistor in some applications.

P1.5/TMS

x = Bit identifier, 4 to 7 for port P1

During programming activity and during blowing

TCK

TST

P1.x

the fuse, the pin TDO/TDI is used to apply the test

input for JTAG circuitry.

P1.4/TCK

Direction

PnSel.x

PnDIR.x

control from

PnOUT.x

Module X OUT

PnIN.x

Module X IN

PnIE.x

PnIFG.x

PnIES.x

module

P1Sel.4

P1DIR.4

P1DIR.4

P1OUT.4

SMCLK

P1IN.4

unused

P1IE.4

P1IFG.4

P1IES.4

P1Sel.5

P1DIR.5

P1DIR.5

P1OUT.5

Out0 signal²

P1IN.5

unused

P1IE.5

P1IFG.5

P1IES.5

P1Sel.6

P1DIR.6

P1DIR.6

P1OUT.6

Out1 signal²

P1IN.6

unused

P1IE.6

P1IFG.6

P1IES.6

P1Sel.7

P1DIR.7

P1DIR.7

P1OUT.7

Out2 signal²

P1IN.7

unused

P1IE.7

P1IFG.7

P1IES.7

² Signal from or to Timer_A

NOTES: 27. Optional selection of pullup or pulldown resistors with ROM (masked) versions.

28. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).

38 POST OFFICE BOX 655303 •DALLAS, TEXAS 75265