Texas Instruments MSP430x11x1 warranty Cpu, Instruction set, Instruction Word Formats

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

short-form description (continued)

CPU

All sixteen registers are located inside the CPU, providing reduced instruction execution time. This reduces a register-register operation execution time to one cycle of the processor.

Program Counter

Stack Pointer

Status Register

PC/R0

SP/R1

SR/CG1/R2

Four registers are reserved for special use as a program counter, a stack pointer, a status register, and a constant generator. The remaining twelve registers are available as general-purpose registers.

Peripherals are connected to the CPU using a data address and control buses and can be handled easily with all instructions for memory manipulation.

instruction set

Constant Generator	CG2/R3
General-Purpose Register	R4
	R5
General-Purpose Register
General-Purpose Register	R14
	R15
General-Purpose Register

The instructions set for this register-register architecture provides a powerful and easy-to-use assembly language. The instruction set consists of 51 instructions with three formats and seven addressing modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing modes are listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination	e.g. ADD R4, R5	R4 + R5 → R5
Single operands, destination only	e.g. CALL R8	PC → (TOS), R8 → PC
Relative jump, un-/conditional	e.g. JNE	Jump-on equal bit = 0

Most instructions can operate on both word and byte data. Byte operations are identified by the suffix B.

Examples:	Instructions for word operation				Instructions for byte operation
	MOV			EDE,TONI	MOV.B	EDE,TONI
	ADD			#235h,&MEM	ADD.B	#35h,&MEM
	PUSH			R5	PUSH.B	R5
	SWPB			R5	Ð
			Table 2. Address Mode Descriptions
ADDRESS MODE	s	d		SYNTAX	EXAMPLE		OPERATION
Register	√	√		MOV Rs, Rd	MOV R10, R11		R10 → R11
Indexed	√	√		MOV X(Rn), Y(Rm)	MOV 2(R5), 6(R6)		M(2 + R5) → M(6 + R6)
Symbolic (PC relative)	√	√		MOV EDE, TONI			M(EDE) → M(TONI)
Absolute	√	√		MOV &MEM, &TCDAT			M(MEM) → M(TCDAT)
Indirect	√			MOV @Rn, Y(Rm)	MOV @R10, Tab(R6)		M(R10) → M(Tab + R6)
Indirect autoincrement	√			MOV @Rn+, RM	MOV @R10+, R11		M(R10) → R11, R10 + 2 → R10
Immediate	√			MOV #X, TONI	MOV #45, TONI		#45 → M(TONI)
NOTE: s = source d = destination		Rs/Rd = source register/destination register Rn = register number

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