Accv, Puc, Por, Nmirs, Irqa | Texas Instruments MSP430x11x1 specification

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

ACCV

ACCVIFG
S
FCTL1.1
ACCVIE				Flash Module
				Flash Module
IE1.5				Flash Module
Clear				Flash Module
				Flash Module
PUC
RST/NMI
				POR	PUC
			KEYV		VCC
						PUC
				System Reset
				Generator
						POR
NMIFG
S						NMIRS
IFG1.4						NMIRS
IFG1.4
Clear	TMSEL	NMI	WDTQn	EQU	PUC	POR
NMIES	TMSEL	NMI	WDTQn	EQU	PUC	POR
PUC
NMIIE
			S	WDTIFG
IE1.4			S			IRQ
IE1.4
Clear		IFG1.0
Clear		IFG1.0
			Clear
PUC		WDT
Counter
OSCFault		POR
		POR
OFIFG
S
IFG1.1
		IRQA
OFIF		TIMSEL
OFIF
				WDTIE
IE1.1
Clear		IE1.0
		IE1.0	Clear
NMI_IRQA			Clear
PUC
Watchdog Timer Module			PUC
Watchdog Timer Module

IRQA: Interrupt Request Accepted

Figure 2. Block Diagram of NMI Interrupt Sources

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Texas Instruments MSP430x11x1 warranty Accv, Puc, Por, Nmirs, Irqa, Timsel

Contents

Tssop MSP430x11x1Description Available Options Packaged Devices Functional block diagramPIN Sowb PIN Tssop Pulldown resistor of 30 k Ω is needed on F11x1 Short-form description Terminal FunctionsProcessing unit Terminal Description Name CPU Address Mode DescriptionsInstruction set Instruction Word Formats Operation modes and interrupts Low-power consumption capabilities SCG1 Status register R2SCG0 SCG1 SCG0 Caifg Interrupt vector addressesWdtifg CCIFG1, CCIFG2, Taifg Wdtifg Special function registersOfifg Nmiifg Memory organization Boot ROM containing bootstrap loaderFunctions of the bootstrap loader Hardware resources used for serial input/output Features of the bootstrap loader areWDT VCC RST/NMI PIN Test PIN VCC Bootstrap loader StartsTest Internal Flash memory control register FCTL1 Flash memory WRT Flash memory, timing generator, control register FCTL2Erase 0128h, bit1, Erase a segment FN0±FN5 Flash memory control register FCTL3SSEL0, SSEL1 Aclk Keyv BusyAccvifg Wait Emex Flash memory, interrupt and security key violationLock PUC AccvPOR Nmirs Oscillator and system clock Peripherals Digital I/O Clock Signals TimerA Three capture/compare registers Watchdog timer TimerA, MSP430x11x1 Configuration TimerA 3 capture/compare registers ComparatorA CAF CaoutCACTL2.4 CATCTL2.7 CACTL1 Slope a/d conversionCaex Caon Caies Caifg Rsel REF1 REF0 CACTL2 Peripheral file map Peripherals with Word AccessPeripherals with Byte Access MIN NOM MAX Units Absolute maximum ratings²Recommended operating conditions Frequency vs Supply Voltage MSP430x11x1 Devices IAM Parameter Test Conditions MIN TYP MAX UnitILPM2 ILPM3 Leakage current Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5 Inputs Px.x, TAx Internal signals TAx, Smclk at TimerAParameter Test Conditions VCC MIN TYP MAX Unit Port P1, P2 P1.x to P2.x ComparatorA see Note Outputs P1.x, P2.x, TAx VRefVT vs Temperature, VCC = 2.2 V, C1121 VRefVT vs Temperature, VCC = 3 V, C1121 CAF Caon PUC/POR Parameter MIN NOM MAX Unit RAM Variance Max DCODcoclk DCO Steps JTAG/programming Principle characteristics of the DCOWake-up from lower power modes LPMx GND Input/output schematicPort P1, P1.0 to P1.3, input/output with Schmitt-trigger P1IFG.4 P1IES.4 P1DIR.4 P1OUT.4 SmclkP1DIR.5 P1OUT.5 P1IFG.5 P1IES.5 CAPD.X Port P2, P2.0 to P2.2, input/output with Schmitt-trigger P2DIR.3 P2OUT.3 Port P2, P2.3 to P2.4, input/output with Schmitt-triggerP2IFG.3 P1IES.3 P2DIR.4 P2OUT.4 P2DIR.5 P2SEL.5 VCCP2OUT.5 P2IRQ.5 Port P2, unbonded bits P2.6 and P2.7 DW R-PDSO-G Pins DIM MAXPlastic SMALL-OUTLINE Package PIN Shown Pins DIM MAX MIN Pins ShownPW R-PDSO-G Plastic SMALL-OUTLINE Package 15 NOM Gage Plane Seating Plane 20 MAX Important Notice

MIXED SIGNAL MICROCONTROLLER

ACCV

PUC

POR

NMIRS

IRQ

IRQA

TIMSEL

Figure 2. Block Diagram of NMI Interrupt Sources