MSP430x11x1
Description
Tssop
PIN Sowb PIN Tssop
Functional block diagram
Available Options Packaged Devices
Pulldown resistor of 30 k Ω is needed on F11x1
Processing unit
Terminal Functions
Short-form description
Terminal Description Name
Instruction set
Address Mode Descriptions
CPU
Instruction Word Formats
Low-power consumption capabilities
Operation modes and interrupts
SCG0
Status register R2
SCG1
SCG1 SCG0
Wdtifg
Interrupt vector addresses
Caifg
CCIFG1, CCIFG2, Taifg
Ofifg
Special function registers
Wdtifg
Nmiifg
Boot ROM containing bootstrap loader
Functions of the bootstrap loader
Memory organization
WDT
Features of the bootstrap loader are
Hardware resources used for serial input/output
VCC RST/NMI PIN Test PIN
Test
Bootstrap loader Starts
VCC
Internal
Flash memory
Flash memory control register FCTL1
Flash memory, timing generator, control register FCTL2
Erase 0128h, bit1, Erase a segment
WRT
SSEL0, SSEL1
Flash memory control register FCTL3
FN0±FN5
Aclk
Accvifg
Busy
Keyv
Wait
Flash memory, interrupt and security key violation
Lock
Emex
POR
Accv
PUC
Nmirs
Peripherals
Oscillator and system clock
Clock Signals
Digital I/O
Watchdog timer
TimerA Three capture/compare registers
TimerA 3 capture/compare registers
TimerA, MSP430x11x1 Configuration
ComparatorA
CACTL2.4
Caout
CAF
CATCTL2.7
Caex Caon Caies Caifg Rsel REF1 REF0
Slope a/d conversion
CACTL1
CACTL2
Peripherals with Word Access
Peripherals with Byte Access
Peripheral file map
Absolute maximum ratings²
Recommended operating conditions
MIN NOM MAX Units
MSP430x11x1 Devices
Frequency vs Supply Voltage
ILPM2
Parameter Test Conditions MIN TYP MAX Unit
IAM
ILPM3
Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5
Leakage current
Parameter Test Conditions VCC MIN TYP MAX Unit
Internal signals TAx, Smclk at TimerA
Inputs Px.x, TAx
Port P1, P2 P1.x to P2.x
Outputs P1.x, P2.x, TAx
ComparatorA see Note
VRefVT vs Temperature, VCC = 3 V, C1121
VRefVT vs Temperature, VCC = 2.2 V, C1121
PUC/POR
CAF Caon
RAM
Parameter MIN NOM MAX Unit
Dcoclk
DCO
Variance Max
DCO Steps
Principle characteristics of the DCO
Wake-up from lower power modes LPMx
JTAG/programming
Input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
GND
P1DIR.5 P1OUT.5
P1DIR.4 P1OUT.4 Smclk
P1IFG.4 P1IES.4
P1IFG.5 P1IES.5
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
CAPD.X
P2IFG.3 P1IES.3
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2DIR.3 P2OUT.3
P2DIR.4 P2OUT.4
P2OUT.5
P2SEL.5 VCC
P2DIR.5
P2IRQ.5
Port P2, unbonded bits P2.6 and P2.7
Plastic SMALL-OUTLINE Package
Pins DIM MAX
DW R-PDSO-G
PIN Shown
PW R-PDSO-G Plastic SMALL-OUTLINE Package
Pins Shown
Pins DIM MAX MIN
15 NOM Gage Plane Seating Plane 20 MAX
Important Notice