Description
MSP430x11x1
Tssop
Available Options Packaged Devices
Functional block diagram
PIN Sowb PIN Tssop
Pulldown resistor of 30 k Ω is needed on F11x1
Short-form description
Terminal Functions
Processing unit
Terminal Description Name
CPU
Address Mode Descriptions
Instruction set
Instruction Word Formats
Operation modes and interrupts
Low-power consumption capabilities
SCG1
Status register R2
SCG0
SCG1 SCG0
Caifg
Interrupt vector addresses
Wdtifg
CCIFG1, CCIFG2, Taifg
Wdtifg
Special function registers
Ofifg
Nmiifg
Functions of the bootstrap loader
Boot ROM containing bootstrap loader
Memory organization
Hardware resources used for serial input/output
Features of the bootstrap loader are
WDT
VCC RST/NMI PIN Test PIN
VCC
Bootstrap loader Starts
Test
Internal
Flash memory control register FCTL1
Flash memory
Erase 0128h, bit1, Erase a segment
Flash memory, timing generator, control register FCTL2
WRT
FN0±FN5
Flash memory control register FCTL3
SSEL0, SSEL1
Aclk
Keyv
Busy
Accvifg
Wait
Lock
Flash memory, interrupt and security key violation
Emex
PUC
Accv
POR
Nmirs
Oscillator and system clock
Peripherals
Digital I/O
Clock Signals
TimerA Three capture/compare registers
Watchdog timer
TimerA, MSP430x11x1 Configuration
TimerA 3 capture/compare registers
ComparatorA
CAF
Caout
CACTL2.4
CATCTL2.7
CACTL1
Slope a/d conversion
Caex Caon Caies Caifg Rsel REF1 REF0
CACTL2
Peripherals with Byte Access
Peripherals with Word Access
Peripheral file map
Recommended operating conditions
Absolute maximum ratings²
MIN NOM MAX Units
Frequency vs Supply Voltage
MSP430x11x1 Devices
IAM
Parameter Test Conditions MIN TYP MAX Unit
ILPM2
ILPM3
Leakage current
Outputs Port 1 to P2 P1.0 to P1.7, P2.0 to P2.5
Inputs Px.x, TAx
Internal signals TAx, Smclk at TimerA
Parameter Test Conditions VCC MIN TYP MAX Unit
Port P1, P2 P1.x to P2.x
ComparatorA see Note
Outputs P1.x, P2.x, TAx
VRefVT vs Temperature, VCC = 2.2 V, C1121
VRefVT vs Temperature, VCC = 3 V, C1121
CAF Caon
PUC/POR
Parameter MIN NOM MAX Unit
RAM
Variance Max
DCO
Dcoclk
DCO Steps
Wake-up from lower power modes LPMx
Principle characteristics of the DCO
JTAG/programming
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
Input/output schematic
GND
P1IFG.4 P1IES.4
P1DIR.4 P1OUT.4 Smclk
P1DIR.5 P1OUT.5
P1IFG.5 P1IES.5
CAPD.X
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
P2DIR.3 P2OUT.3
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2IFG.3 P1IES.3
P2DIR.4 P2OUT.4
P2DIR.5
P2SEL.5 VCC
P2OUT.5
P2IRQ.5
Port P2, unbonded bits P2.6 and P2.7
DW R-PDSO-G
Pins DIM MAX
Plastic SMALL-OUTLINE Package
PIN Shown
Pins DIM MAX MIN
Pins Shown
PW R-PDSO-G Plastic SMALL-OUTLINE Package
15 NOM Gage Plane Seating Plane 20 MAX
Important Notice