MSP430x11x1
MIXED SIGNAL MICROCONTROLLER
SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000
flash memory control register FCTL1 (continued)
Read access is possible at any time without restrictions.
The control bits of control register FCTL1 are:
15
FCTL1
0128h
8 | 7 |
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| SEG | WRT | res. | res. | res. | MEras | Erase | res. |
| WRT | |||||||
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| rw±0 rw±0 | r0 | r0 | r0 | rw±0 | r0 | ||
FCTL1 read: |
| 096h |
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FCTL1 write: |
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| 0A5h |
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Erase | 0128h, bit1, Erase a segment | ||
0:No segment erase will be started.
1:Erase of one segment is enabled. The segment to be erased is defined by a dummy write into any address within the segment. The erase bit is automatically reset when the erase operation is completed.
MEras | 0128h, bit2, Mass Erase, main memory segments are erased together. |
0:No segment erase will be started.
1:Erase of main memory segments is enabled. Erase starts when a dummy write to any address in main memory is executed. The MEras bit is automatically reset when the erase operation is completed.
WRT | 0128h, bit6, Bit WRT must be set for a successful write execution. |
If bit WRT is reset and write access to the flash memory is attempted, an access violation occurs and ACVIFG is set.
SEGWRT 0128h, bit7, Bit SEGWRT may be used to reduce total programming time.
Refer to MSP430x1xx User's Guide, literature number SLAU049 for details.
0:No
1:
Table 3. Allowed Combinations of Control Bits Allowed for Flash Memory Access
FUNCTION PERFORMED | SEGWRT | WRT | MEras | Erase | BUSY | WAIT | Lock |
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Write word or byte | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
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Write word or byte in same segment, segment write mode | 1 | 1 | 0 | 0 | 0 → 1 | 0 → 1 | 0 |
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Erase one segment by writing to any address in the target segment | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
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Erase all segments (0 to 7) but not the information memory | 0 | 0 | 1 | 0 | 0 | 0 | 0 |
(segments A and B) |
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Erase all segments (0 to 7 and A and B) by writing to any address in | 0 | 0 | 1 | 1 | 0 | 0 | 0 |
the flash memory module |
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NOTE: The table shows all valid combinations. Any other combination will result in an access violation.
flash memory, timing generator, control register FCTL2
The timing generator (Figure 1) generates all the timing signals necessary for write, erase, and mass erase from the selected clock source. One of three different clock sources may be selected by control bits SSEL0 and SSEL1 in control register FCTL2. The selected clock source should be divided to meet the frequency requirements specified in the recommended operating conditions.
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