Texas Instruments MSP430x11x1 outputs P1.x, P2.x, TAx, ComparatorA see Note, t res ponse HL

MSP430x11x1

MIXED SIGNAL MICROCONTROLLER

SLAS241C ± SEPTEMBER 1999 ± REVISED JUNE 2000

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

outputs P1.x, P2.x, TAx

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

f(P20)

P2.0/ACLK,

CL = 20 pF

2.2 V/3 V

fSystem

f(TAx)

Output frequency

TA0, TA1, TA2,

CL = 20 pF

2.2 V/3 V

dc

fSystem

MHz

Internal clock source, SMCLK signal applied (see Note 16)

fSMCLK = fLFXT1 = fXT1

40%

60%

P1.4/SMCLK,

fSMCLK = fLFXT1 = fLF

2.2 V/3 V

35%

65%

50%±

50%+

CL = 20 pF

f

SMCLK

= f

LFXT1/n

50%

15 ns

15 ns

t(Xdc)

Duty cycle of O/P

fSMCLK = fDCOCLK

2.2 V/3 V

50%±

50%

50%+

frequency

15 ns

15 ns

P2.0/ACLK,

fP20 = fLFXT1 = fXT1

40%

60%

fP20 = fLFXT1 = fLF

2.2 V/3 V

30%

70%

CL = 20 pF

fP20 = fLFXT1/n

50%

t(TAdc)

TA0, TA1, TA2,

CL = 20 pF,

Duty cycle = 50%

2.2 V/3 V

0

±50

ns

NOTE 16: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.

Comparator_A (see Note 17)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I(DD)

CAON=1,

CARSEL=0, CAREF=0

VCC = 2.2 V

25

40

∝A

VCC = 3 V

45

60

I(Refladder/

CAON=1,

CARSEL=0,

VCC = 2.2 V

30

50

CAREF=1/2/3, No load at

∝A

RefDiode)

VCC = 3 V

45

71

P2.3/CA0/TA1 and P2.4/CA1/TA2

V(IC)

Common-mode input

CAON =1

VCC = 2.2 V/3 V

0

VCC±1

V

voltage

V(Ref025)

Voltage @ 0.25 VCC

node

PCA0=1,

CARSEL=1, CAREF=1,

No load at P2.3/CA0/TA1 and

VCC = 2.2 V/3 V

0.23

0.24

0.25

See Figure 5

VCC

P2.4/CA1/TA2, See Figure 5

V(Ref050)

Voltage @ 0.5 VCC node

PCA0=1,

CARSEL=1, CAREF=2,

No load at P2.3/CA0/TA1 and

VCC = 2.2 V/3 V

0.47

0.48

0.5

See Figure 5

VCC

P2.4/CA1/TA2, See Figure 5

PCA0=1,

CARSEL=1, CAREF=3,

VCC = 2.2 V

430

550

645

V(RefVT)

No load at P2.3/CA0/TA1 and

mV

VCC = 3 V

450

565

660

P2.4/CA1/TA2

V(offset)

Offset voltage

See Note 18

VCC = 2.2 V/3 V

±30

30

mV

Vhys

Input hysteresis

CAON=1

VCC = 2.2 V/3 V

0

0.7

1.4

mV

°

V

CC

= 2.2 V

160

210

300

TA = 25 C, Overdrive 10 mV, With-

ns

out filter:

CAF=0

VCC = 3 V

90

150

200

t(response LH)

°

V

CC

= 2.2 V

1.6

1.9

3.4

TA = 25 C, Overdrive 10 mV, With

∝s

filter: CAF=1

VCC = 3 V

1.1

1.5

2.6

TA = 25°C,

V

CC

= 2.2 V

160

210

300

Overdrive 10 mV, without filter:

ns

VCC = 3 V

90

150

200

t(response HL)

CAF=0

°

V

CC

= 2.2 V

1.6

1.9

3.4

TA = 25 C,

∝s

Overdrive 10 mV, with filter: CAF=1

VCC = 3 V

1.1

1.5

2.6

NOTES: 17. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.

18.The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.

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