Texas Instruments TMS320C64X manual DSPfft16x16r

DSP_fft16x16r

void dft(int n, short x[], short y[])

{

int k,i, index;

const double PI = 3.14159654; short * p_x;

double arg, fx_0, fx_1, fy_0, fy_1, co, si;

for(k = 0; k<n; k++)

{

p_x = x; fy_0 = 0; fy_1 = 0; for(i=0; i<n; i++)

{

fx_0 = (double)p_x[0]; fx_1 = (double)p_x[1]; p_x += 2;

index = (i*k) % n; arg = 2*PI*index/n; co = cos(arg);

si = −sin(arg);

fy_0 += ((fx_0 * co) − (fx_1 * si)); fy_1 += ((fx_1 * co) + (fx_0 * si));

}

y[2*k] = (short)2*fy_0/sqrt(n); y[2*k+1] = (short)2*fy_1/sqrt(n);

}

}

Scaling by 2 (i.e., >>1) takes place at each radix-4 stage except the last one. A radix-4 stage could give a maximum bit-growth of 2 bits, which would require scaling by 4. To completely prevent overflow, the input data must be scaled by 2(BT−BS), where BT (total number of bit growth) = log2(nx) and BS (number of scales by the functions) = ceil[log4(nx)−1]. All shifts are rounded to reduce truncation noise power by 3dB.

C64x+ DSPLIB Reference 4-15