Texas Instruments TMS320C64X manual Values in a single clock cycle

DSP_fir_r4

Special Requirements

-The number of coefficients, nh, must be a multiple of 4 and greater than or equal to 8. Coefficients must be in reverse order.

-The number of outputs computed, nr, must be a multiple of 4 and greater than or equal to 4.

Implementation Notes

	- Bank Conflicts: No bank conflicts occur.
	- Interruptibility: The code is interrupt-tolerant but not interruptible.
	- The load double-word instruction is used to simultaneously load four
	values in a single clock cycle.
	- The inner loop is unrolled four times and will always compute a multiple
	of 4 output samples.
Benchmarks	Cycles	(8 + nh) * nr/4 + 9
	Codesize	308 bytes

C64x+ DSPLIB Reference 4-47