Texas Instruments TMS320C64X manual A single clock cycle

DSP_fir_gen

Special Requirements

-The number of coefficients, nh, must be greater than or equal to 5. Coefficients must be in reverse order.

-The number of outputs computed, nr, must be a multiple of 4 and greater than or equal to 4.

-Array r[ ] must be word aligned.

Implementation Notes

	- Bank Conflicts: No bank conflicts occur.
	- Interruptibility: The code is interrupt-tolerant but not interruptible.
	- Load double-word instruction is used to simultaneously load four values
	in a single clock cycle.
	- The inner loop is unrolled four times and will always compute a multiple
	of 4 of nh and nr. If nh is not a multiple of 4, the code will fill in zeros to make
	nh a multiple of 4.
	- This code yields best performance when the ratio of outer loop to inner
	loop is less than or equal to 4.
Benchmarks	Cycles: Not available
	Codesize: Not available

C64x+ DSPLIB Reference 4-43