DSP_iirlat
rt | = | rt | − | (short)(b[i] >> | 15) | * | k[i]; |
b[i + 1] = | b[i] | + | (short)(rt >> | 15) | * | k[i]; | |
}
b[0] = rt;
r[j] = rt >> 15;
}
}
Special Requirements
-nk must be >= 4.
-No special alignment requirements
-See Bank Conflicts for avoiding bank conflicts
Implementation Notes
-Bank Conflicts: nk should be a multiple of 2, otherwise bank conflicts occur.
-Interruptibility: The code is
-Prolog and epilog of the inner loop are partially collapsed and overlapped to reduce outer loop overhead.
Benchmarks | Cycles | (2 * nk + 7) * nx + 9 | (without bank conflicts) |
| Codesize | 352 bytes |
|
C64x+ DSPLIB Reference |
