Rhsc FNO WDH | Texas Instruments TMS320C6747 DSP instruction

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3.4HC Interrupt and Status Register (HCINTERRUPTSTATUS)

The HC interrupt and status register (HCINTERRUPTSTATUS) reports the status of the USB host controller internal interrupt sources. HCINTERRUPTSTATUS is shown in Figure 5 and described in Table 5.

Figure 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS)

31	30	29								16
Rsvd	OC			Reserved
R-0	R-0			R-0
15			7	6	5	4	3	2	1	0
		Reserved		RHSC	FNO	UE	RD	SF	WDH	SO
		R-0		R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0 R/W1C-0
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n= value after reset

Table 5. HC Interrupt and Status Register (HCINTERRUPTSTATUS) Field Descriptions

Bit	Field	Value	Description
31	Reserved	0	Reserved
30	OC	0-1	Ownership change.
29-7	Reserved	0	Reserved
6	RHSC		Root hub status change. A write of 1 clears this bit; a write of 0 has no effect.
		0	A root hub status change has not occurred.
		1	A root hub status change has occurred.
5	FNO		Frame number overflow. A write of 1 clears this bit; a write of 0 has no effect.
		0	A frame number overflow has not occurred.
		1	A frame number overflow has occurred.
4	UE		Unrecoverable error. A write of 1 clears this bit; a write of 0 has no effect.
		0	An unrecoverable error has not occurred.

1An unrecoverable error has occurred on the OCPI bus, or that an isochronous TD PSW field condition code was not set to Not Accessed when the USB host controller attempted to perform a transfer using that PSW/offset pair.

3	RD	Resume detected. A write of 1 clears this bit; a write of 0 has no effect.
	0	A downstream device has not issued a resume request.
	1	A downstream device has issued a resume request.
2	SF	Start of frame. A write of 1 clears this bit; a write of 0 has no effect.
	0	A SOF has not been issued.
	1	A SOF has been issued.
1	WDH	Write done head. The host controller driver must read the value from the HC head done register
		(HCDONEHEAD) before writing 1 to this bit. A write of 1 clears this bit; a write of 0 has no effect.
	0	USB host controller has not updated the HC head done register (HCDONEHEAD).
	1	USB host controller has updated the HC head done register (HCDONEHEAD).
0	SO	Scheduling overrun. A write of 1 clears this bit; a write of 0 has no effect.
	0	A scheduling overrun has not occurred.
	1	A scheduling overrun has occurred.

16	Universal Serial Bus OHCI Host Controller	SPRUFM8–September 2008
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Texas Instruments TMS320C6747 DSP manual HC Interrupt and Status Register Hcinterruptstatus, Rhsc FNO WDH

Contents

Users Guide Literature Number SPRUFM8 September SPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the Peripheral USB1 Module Clock and Reset 2 USB1 Module Local Bus Clock and Local ResetInternal System Bus Clocks Needed by the USB1 Module 3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface Functionality Implementation of Ohci Specification for USB Ohci USB Suspend State USB Host Controller Access to System Memory Ohci InterruptsPhysical Addressing MMU USB Host Controller Registers HC Operating Mode Register Hccontrol Ohci Revision Number Register HcrevisionOhci Revision Number Register Hcrevision Field Descriptions REV Control list enable Periodic list enableControl ED per bulk ED Control EDs per bulk ED HC Command and Status Register Hccommandstatus SOCOCR BLF CLF HCR OCR Rhsc FNO WDH HC Interrupt and Status Register HcinterruptstatusRhsc HC Interrupt Enable Register Hcinterruptenable MIE HC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca HC Current Periodic Register HcperiodcurrentedHC Hcaa Address Register Hchcca Field Descriptions Hcca HC Head Control Register Hccontrolheaded Field Descriptions HC Head Control Register HccontrolheadedChed Cced HC Current Control Register HccontrolcurrentedController HC Head Bulk Register Hcbulkheaded HC Current Bulk Register HcbulkcurrentedHC Head Bulk Register Hcbulkheaded Field Descriptions HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Done Register Hcdonehead HC Frame Interval Register HcfmintervalHC Head Done Register Hcdonehead Field Descriptions HC Frame Interval Register Hcfminterval Field Descriptions HC Frame Remaining Register Hcfmremaining HC Frame Number Register HcfmnumberHC Frame Number Register Hcfmnumber Field Descriptions FRT HC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart HC Low-Speed Threshold Register Hclsthreshold LST628h Reserved 13-0 HC Root Hub a Register Hcrhdescriptora HC Root Hub a Register Hcrhdescriptora Field DescriptionsPotpg Nocp Ocpm NPS PSM NDP HC Root Hub B Register Hcrhdescriptorb HC Root Hub B Register Hcrhdescriptorb Field DescriptionsPPCM3 PPCM2 PPCM1 PPCM0 PPCM3 HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field Descriptions HC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changed When read as 0, USB reset is not being sent to port Begin signaling USB reset to portEnd of the USB reset sequence Write of 1 to this bit clears the port 2 port enable bit DSP Rfid