www.ti.comRegisters
Table 23. HC Port 1 Status and Control Register (HCRHPORTSTATUS1) Field Descriptions (continued)
Bit | Field | Value | Description |
8 | PPS/SPP |
| Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set the |
|
|
| port 1 port power status bit; a write of 0 has no effect. The device does not provide signals from the |
|
|
| USB host controller to control external port power, so if required, USB host port power control |
|
|
| signals must be controlled through other means. Software can track the current power state using |
|
|
| the port power status bit and other power control bits, but those bits have no direct effect on |
|
|
| external port power control. This bit has no relationship to the OTG controller register bits that relate |
|
|
| to VBUS. System software can update this register to simplify host controller driver and/or OTG |
|
|
| driver coding. |
|
| 0 | Port 1 power is disabled. |
|
| 1 | Port 1 power is enabled. |
Reserved | 0 | Reserved | |
4 | PRS/SPR |
| Port 1 port reset status/set port reset. A write of 1 to this bit sets the port 1 port reset status bit and |
|
|
| causes the USB host controller to begin signaling USB reset to port 1; a write of 0 has no effect. |
|
| 0 | USB reset is not being sent to port 1. |
|
| 1 | Port 1 is signaling the USB reset. |
3 | POCI/CSS |
| Port 1 port overcurrent indicator/clear suspend status. A write of 1 to this bit when port 1 port |
|
|
| suspend status is 1 causes resume signaling on port 1; a write of 1 when port 1 port suspend |
|
|
| status is 0 has no effect; a write of 0 has no effect. The device does not provide inputs for signaling |
|
|
| external overcurrent indication to the USB host controller. Overcurrent monitoring, if required, must |
|
|
| be handled through some other mechanism. |
|
| 0 | Port 1 port overcurrent condition has not occurred. |
|
| 1 | Port 1 port overcurrent condition has occurred. |
2 | PSS/SPS |
| Port 1 port suspend status/set port suspend. A write of 1 to this bit when port 1 current connect |
|
|
| status is 1 sets the port 1 port suspend status bit and places port 1 in USB suspend state; a write of |
|
|
| 1 when port 1 current connect status is 0 sets the connect status change to inform the USB host |
|
|
| controller driver software of an attempt to suspend a disconnected device; a write of 0 has no |
|
|
| effect. This bit is cleared automatically at the end of the USB resume sequence and also at the end |
|
|
| of the USB reset sequence. |
|
| 0 | Port 1 is not in the USB suspend state. |
|
| 1 | Port 1 is in the USB suspend state or is in the resume sequence. |
1 | PES/SPE |
| Port 1 port enable status/set port enable. A write of 1 to this bit when port 1 current connect status |
|
|
| is 1 sets the port 1 port enable status bit; a write of 1 when port 1 current connect status is 0 has no |
|
|
| effect; a write of 0 has no effect. This bit is automatically set at completion of port 1 USB reset, if it |
|
|
| was not already set before the USB reset completed; and this bit is automatically set at the end of a |
|
|
| USB suspend, if the port was not enabled when the USB resume completed. |
|
| 0 | Port 1 is disabled. |
|
| 1 | Port 1 is enabled. |
0 | CCS/CPE |
| Port 1 current connection status/clear port enable. If the DR[1] bit in the HC root hub B register |
|
|
| (HCRHDESCRIPTORB) is set to 1 to indicate a nonremovable USB device on port 1, this bit is set |
|
|
| after a root hub reset to inform the system that the device is attached. A write of 1 clears this bit; a |
|
|
| write of 0 has no effect. |
|
| 0 | No USB device is attached to port 1. |
|
| 1 | USB device is attached to port 1. |
Universal Serial Bus OHCI Host Controller | 31 | |
Submit Documentation Feedback |
|
|
