Manuals / Texas Instruments / Computer Equipment / Network Card

Texas Instruments TMS320C6747 DSP manual HC Low-Speed Threshold Register Hclsthreshold, Lst, 628h

Models: TMS320C6747 DSP

1 34

Download 34 pages 39.94 Kb

Page 26

Image 26

Registers

www.ti.com

3.18 HC Low-Speed Threshold Register (HCLSTHRESHOLD)

The HC low-speed threshold register (HCLSTHRESHOLD) defines the latest time in a frame that the USB host controller can begin a low-speed packet. HCLSTHRESHOLD is shown in Figure 19 and described in Table 19.

			Figure 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD)
31			16
			Reserved
			R-0
15	14	13	0
Reserved			LST
	R-0		R/W-628h

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 19. HC Low-Speed Threshold Register (HCLSTHRESHOLD) Field Descriptions

Bit	Field	Value	Description
31-14	Reserved	0	Reserved
13-0	LST	0-3FFFh	Low-speed threshold. This field defines the number of full-speed bit times in the frame after which
			the USB host controller cannot start an 8-byte low-speed packet. The USB host controller only
			begins a low-speed transaction if the frame remaining (FR) value in the HC frame remaining
			register (HCFMREMAINING) is greater than the low-speed threshold.

The host controller driver must set this field to a value that ensures that an 8-byte low-speed TD completes before the end of the frame. When set, the host controller driver must not change the value.

26

Universal Serial Bus OHCI Host Controller

SPRUFM8–September 2008

Submit Documentation Feedback

Image 26

Texas Instruments TMS320C6747 DSP manual HC Low-Speed Threshold Register Hclsthreshold, Lst, 628h, Reserved 13-0

Contents

Users Guide Literature Number SPRUFM8 September SPRUFM8-September Contents List of Figures List of Tables Read This First Universal Serial Bus Ohci Host Controller Purpose of the Peripheral Internal System Bus Clocks Needed by the USB1 Module USB1 Module Clock and Reset2 USB1 Module Local Bus Clock and Local Reset 3 USB1 Module Bus 48-MHz Reference Clock USB1 Module Differences From Ohci Specification for USB USB1 Module Open Host Controller Interface Functionality Implementation of Ohci Specification for USB Ohci USB Suspend State Physical Addressing USB Host Controller Access to System MemoryOhci Interrupts MMU USB Host Controller Registers Ohci Revision Number Register Hcrevision Field Descriptions HC Operating Mode Register HccontrolOhci Revision Number Register Hcrevision REV Control ED per bulk ED Control list enablePeriodic list enable Control EDs per bulk ED OCR BLF CLF HCR HC Command and Status Register HccommandstatusSOC OCR Rhsc HC Interrupt and Status Register HcinterruptstatusRhsc FNO WDH HC Interrupt Enable Register Hcinterruptenable MIE HC Interrupt Disable Register Hcinterruptdisable HC Hcaa Address Register Hchcca Field Descriptions HC Hcaa Address Register HchccaHC Current Periodic Register Hcperiodcurrented Hcca Ched HC Head Control Register HccontrolheadedHC Head Control Register Hccontrolheaded Field Descriptions Controller HC Current Control Register HccontrolcurrentedCced HC Head Bulk Register Hcbulkheaded Field Descriptions HC Head Bulk Register HcbulkheadedHC Current Bulk Register Hcbulkcurrented HC Current Bulk Register Hcbulkcurrented Field Descriptions HC Head Done Register Hcdonehead Field Descriptions HC Head Done Register HcdoneheadHC Frame Interval Register Hcfminterval HC Frame Interval Register Hcfminterval Field Descriptions HC Frame Number Register Hcfmnumber Field Descriptions HC Frame Remaining Register HcfmremainingHC Frame Number Register Hcfmnumber FRT HC Periodic Start Register Hcperiodicstart HC Periodic Start Register Hcperiodicstart 628h HC Low-Speed Threshold Register HclsthresholdLST Reserved 13-0 Potpg HC Root Hub a Register HcrhdescriptoraHC Root Hub a Register Hcrhdescriptora Field Descriptions Nocp Ocpm NPS PSM NDP PPCM3 PPCM2 PPCM1 PPCM0 HC Root Hub B Register HcrhdescriptorbHC Root Hub B Register Hcrhdescriptorb Field Descriptions PPCM3 HC Root Hub Status Register Hcrhstatus HC Root Hub Status Register Hcrhstatus Field Descriptions HC Port 1 Status and Control Register HCRHPORTSTATUS1 PRS/SPR HC Port 2 Status and Control Register HCRHPORTSTATUS2 Effect Port 2 current connect status has not changed End of the USB reset sequence When read as 0, USB reset is not being sent to portBegin signaling USB reset to port Write of 1 to this bit clears the port 2 port enable bit DSP Rfid