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Texas Instruments TMS320C6747 DSP HC Interrupt Disable Register HCINTERRUPTDISABLE, Registers

Models: TMS320C6747 DSP

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3.6HC Interrupt Disable Register (HCINTERRUPTDISABLE)

Registers

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3.6HC Interrupt Disable Register (HCINTERRUPTDISABLE)

The HC interrupt disable register (HCINTERRUPTDISABLE) is used to clear bits in the HC interrupt enable register (HCINTERRUPTENABLE). HCINTERRUPTDISABLE is shown in Figure 7 and described in Table 7.

Figure 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE)

31	30	29								16
MIE	OC		Reserved
R/W-0	R-0			R-0
15			7	6	5	4	3	2	1	0
		Reserved		RHSC	FNO	UE	RD	SF	WDH	SO
		R-0		R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 7. HC Interrupt Disable Register (HCINTERRUPTDISABLE) Field Descriptions

Bit	Field	Value	Description
31	MIE		Master interrupt enable. Read always returns 0.
		0	No effect.
		1	Clears the MIE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
30	OC	0-1	Ownership change.
29-7	Reserved	0	Reserved
6	RHSC		Root hub status change. Read always returns 0.
		0	No effect.
		1	Clears the RHSC bit in the HC interrupt enable register (HCINTERRUPTENABLE).
5	FNO		Frame number overflow. Read always returns 0.
		0	No effect.
		1	Clears the FNO bit in the HC interrupt enable register (HCINTERRUPTENABLE).
4	UE		Unrecoverable error. Read always returns 0.
		0	No effect.
		1	Clears the UE bit in the HC interrupt enable register (HCINTERRUPTENABLE).
3	RD		Resume detected. Read always returns 0.
		0	No effect.
		1	Clears the RD bit in the HC interrupt enable register (HCINTERRUPTENABLE).
2	SF		Start of frame. Read always returns 0.
		0	No effect.
		1	Clears the SF bit in the HC interrupt enable register (HCINTERRUPTENABLE).
1	WDH		Write done head. Read always returns 0.
		0	No effect.
		1	Clears the WDH bit in the HC interrupt enable register (HCINTERRUPTENABLE).
0	SO		Scheduling overrun. Read always returns 0.
		0	No effect.
		1	Clears the SO bit in the HC interrupt enable register (HCINTERRUPTENABLE).

18	Universal Serial Bus OHCI Host Controller	SPRUFM8–September 2008
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Texas Instruments TMS320C6747 DSP HC Interrupt Disable Register HCINTERRUPTDISABLE, Registers, Field, Value, Description

Contents

Users Guide TMS320C6747 DSP Universal Serial Bus USB OHCI Host ControllerSPRUFM8-September Submit Documentation FeedbackContents List of Figures List of Tables USB Host Controller RegistersHC HCAA Address Register HCHCCA Field Descriptions About This Manual Read This FirstPreface Notational Conventions1 Introduction Universal Serial Bus OHCI Host ControllerUsers Guide 1.1 Purpose of the Peripheral2 Architecture 2.1 USB1 Module Clock and Reset2.1.2 USB1 Module Local Bus Clock and Local Reset 2.1.1 Internal System Bus Clocks Needed by the USB1 Module2.3.2 Overcurrent Protection Input Pins Not Supported 2.3 USB1 Module Differences From OHCI Specification for USB2.3.1 Power Switching Output Pins Not Supported 2.2 USB1 Module Open Host Controller Interface Functionality2.4 Implementation of OHCI Specification for USB 2.4.1 USB Host Controller Endpoint Descriptor ED List Head Pointers2.4.2 OHCI USB Suspend State 2.7 Physical Addressing 2.6 USB Host Controller Access to System Memory2.5 OHCI Interrupts Figure 1. Relationships Between Virtual Address Physical Address3 Registers Table 1. USB Host Controller Registers3.1 OHCI Revision Number Register HCREVISION 3.2 HC Operating Mode Register HCCONTROLFigure 3. HC Operating Mode Register HCCONTROL Figure 2. OHCI Revision Number Register HCREVISIONValue Table 3. HC Operating Mode Register HCCONTROL Field DescriptionsField DescriptionField 3.3 HC Command and Status Register HCCOMMANDSTATUSFigure 4. HC Command and Status Register HCCOMMANDSTATUS ValueRegisters 3.4 HC Interrupt and Status Register HCINTERRUPTSTATUSFigure 5. HC Interrupt and Status Register HCINTERRUPTSTATUS FieldField 3.5 HC Interrupt Enable Register HCINTERRUPTENABLEFigure 6. HC Interrupt Enable Register HCINTERRUPTENABLE Value DescriptionRegisters 3.6 HC Interrupt Disable Register HCINTERRUPTDISABLEFigure 7. HC Interrupt Disable Register HCINTERRUPTDISABLE FieldFigure 8. HC HCAA Address Register HCHCCA 3.7 HC HCAA Address Register HCHCCA3.8 HC Current Periodic Register HCPERIODCURRENTED Table 8. HC HCAA Address Register HCHCCA Field DescriptionsTable 10. HC Head Control Register HCCONTROLHEADED Field Descriptions 3.9 HC Head Control Register HCCONTROLHEADEDFigure 10. HC Head Control Register HCCONTROLHEADED RegistersField 3.10 HC Current Control Register HCCONTROLCURRENTEDFigure 11. HC Current Control Register HCCONTROLCURRENTED DescriptionFigure 12. HC Head Bulk Register HCBULKHEADED 3.11 HC Head Bulk Register HCBULKHEADED3.12 HC Current Bulk Register HCBULKCURRENTED Table 12. HC Head Bulk Register HCBULKHEADED Field DescriptionsFigure 14. HC Head Done Register HCDONEHEAD 3.13 HC Head Done Register HCDONEHEAD3.14 HC Frame Interval Register HCFMINTERVAL Table 14. HC Head Done Register HCDONEHEAD Field DescriptionsFigure 16. HC Frame Remaining Register HCFMREMAINING 3.15 HC Frame Remaining Register HCFMREMAINING3.16 HC Frame Number Register HCFMNUMBER Figure 17. HC Frame Number Register HCFMNUMBERField 3.17 HC Periodic Start Register HCPERIODICSTARTFigure 18. HC Periodic Start Register HCPERIODICSTART ValueRegisters 3.18 HC Low-Speed Threshold Register HCLSTHRESHOLDFigure 19. HC Low-Speed Threshold Register HCLSTHRESHOLD FieldTable 20. HC Root Hub A Register HCRHDESCRIPTORA Field Descriptions 3.19 HC Root Hub A Register HCRHDESCRIPTORAFigure 20. HC Root Hub A Register HCRHDESCRIPTORA FieldTable 21. HC Root Hub B Register HCRHDESCRIPTORB Field Descriptions 3.20 HC Root Hub B Register HCRHDESCRIPTORBFigure 21. HC Root Hub B Register HCRHDESCRIPTORB RegistersTable 22. HC Root Hub Status Register HCRHSTATUS Field Descriptions 3.21 HC Root Hub Status Register HCRHSTATUSFigure 22. HC Root Hub Status Register HCRHSTATUS FieldRegisters 3.22 HC Port 1 Status and Control Register HCRHPORTSTATUS1Figure 23. HC Port 1 Status and Control Register HCRHPORTSTATUS1 FieldDescription Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set theField Submit Documentation FeedbackRegisters 3.23 HC Port 2 Status and Control Register HCRHPORTSTATUS2Figure 24. HC Port 2 Status and Control Register HCRHPORTSTATUS2 FieldField DescriptionSubmit Documentation Feedback IMPORTANT NOTICE ProductsApplications