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Texas Instruments TMS320C6747 DSP manual HC Interrupt Enable Register HCINTERRUPTENABLE, Field

Models: TMS320C6747 DSP

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3.5HC Interrupt Enable Register (HCINTERRUPTENABLE)

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Registers

3.5HC Interrupt Enable Register (HCINTERRUPTENABLE)

The HC interrupt enable register (HCINTERRUPTENABLE) enables various OHCI interrupt sources to generate interrupts to the level 2 interrupt controller. HCINTERRUPTENABLE is shown in Figure 6 and described in Table 6.

Figure 6. HC Interrupt Enable Register (HCINTERRUPTENABLE)

31	30	29								16
MIE	OC			Reserved
R/W1S-0 R-0				R-0
15			7	6	5	4	3	2	1	0
		Reserved		RHSC	FNO	UE	RD	SF	WDH	SO
		R-0		R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0 R/W1S-0
LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing 0 has no effect); -n= value after reset

		Table 6. HC Interrupt Enable Register (HCINTERRUPTENABLE) Field Descriptions
Bit	Field	Value Description
31	MIE	Master interrupt enable. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
		corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.

0OHCI interrupt sources are ignored and USB host controller interrupts are not propagated to the level 2 interrupt controller.

		1	Allows other enabled OHCI interrupt sources to propagate to the level 2 interrupt controller.
30	OC	0-1	Ownership change.
29-7	Reserved	0	Reserved
6	RHSC		Root hub status change. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
			corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Root hub status change interrupts do not propagate.
		1	When MIE is 1, allows root hub status change interrupts to propagate to the level 2 interrupt controller.
5	FNO		Frame number overflow. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
			corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Frame number overflow interrupts do not propagate.
		1	When MIE is 1, allows frame number overflow interrupts to propagate to the level 2 interrupt controller.
4	UE		Unrecoverable error. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the
			corresponding bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Unrecoverable error interrupts do not propagate.
		1	When MIE is 1, allows unrecoverable error interrupts to propagate to the level 2 interrupt controller.
3	RD		Resume detected. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
			bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Resume detected interrupts do not propagate.
		1	When MIE is 1, allows resume detected interrupts to propagate to the level 2 interrupt controller.
2	SF		Start of frame. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding bit in
			the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Start of frame interrupts do not propagate.
		1	When MIE is 1, allows start of frame interrupts to propagate to the level 2 interrupt controller.
1	WDH		Write done head. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
			bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Write done head interrupts do not propagate.
		1	When MIE is 1, allows write done head interrupts to propagate to the level 2 interrupt controller.
0	SO		Scheduling overrun. A write of 1 sets this bit; a write of 0 has no effect. A write of 1 to the corresponding
			bit in the HC interrupt disable register (HCINTERRUPTDISABLE) clears this bit.
		0	Scheduling overrun interrupts do not propagate.
		1	When MIE is 1, allows scheduling overrun interrupts to propagate to the level 2 interrupt controller.
SPRUFM8–September 2008			Universal Serial Bus OHCI Host Controller	17
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Texas Instruments TMS320C6747 DSP manual HC Interrupt Enable Register HCINTERRUPTENABLE, Field, Value Description

Contents

TMS320C6747 DSP Universal Serial Bus USB OHCI Host Controller Users GuideSubmit Documentation Feedback SPRUFM8-SeptemberContents List of Figures HC HCAA Address Register HCHCCA Field Descriptions List of TablesUSB Host Controller Registers Preface Read This FirstAbout This Manual Notational ConventionsUsers Guide Universal Serial Bus OHCI Host Controller1 Introduction 1.1 Purpose of the Peripheral2.1.2 USB1 Module Local Bus Clock and Local Reset 2.1 USB1 Module Clock and Reset2 Architecture 2.1.1 Internal System Bus Clocks Needed by the USB1 Module2.3.1 Power Switching Output Pins Not Supported 2.3 USB1 Module Differences From OHCI Specification for USB2.3.2 Overcurrent Protection Input Pins Not Supported 2.2 USB1 Module Open Host Controller Interface Functionality2.4.2 OHCI USB Suspend State 2.4 Implementation of OHCI Specification for USB2.4.1 USB Host Controller Endpoint Descriptor ED List Head Pointers 2.5 OHCI Interrupts 2.6 USB Host Controller Access to System Memory2.7 Physical Addressing Figure 1. Relationships Between Virtual Address Physical AddressTable 1. USB Host Controller Registers 3 Registers3.2 HC Operating Mode Register HCCONTROL 3.1 OHCI Revision Number Register HCREVISIONFigure 2. OHCI Revision Number Register HCREVISION Table 2. OHCI Revision Number Register HCREVISION Field DescriptionsField Table 3. HC Operating Mode Register HCCONTROL Field DescriptionsValue DescriptionFigure 4. HC Command and Status Register HCCOMMANDSTATUS 3.3 HC Command and Status Register HCCOMMANDSTATUSField ValueFigure 5. HC Interrupt and Status Register HCINTERRUPTSTATUS 3.4 HC Interrupt and Status Register HCINTERRUPTSTATUSRegisters FieldFigure 6. HC Interrupt Enable Register HCINTERRUPTENABLE 3.5 HC Interrupt Enable Register HCINTERRUPTENABLEField Value DescriptionFigure 7. HC Interrupt Disable Register HCINTERRUPTDISABLE 3.6 HC Interrupt Disable Register HCINTERRUPTDISABLERegisters Field3.8 HC Current Periodic Register HCPERIODCURRENTED 3.7 HC HCAA Address Register HCHCCAFigure 8. HC HCAA Address Register HCHCCA Table 8. HC HCAA Address Register HCHCCA Field DescriptionsFigure 10. HC Head Control Register HCCONTROLHEADED 3.9 HC Head Control Register HCCONTROLHEADEDTable 10. HC Head Control Register HCCONTROLHEADED Field Descriptions RegistersFigure 11. HC Current Control Register HCCONTROLCURRENTED 3.10 HC Current Control Register HCCONTROLCURRENTEDField Description3.12 HC Current Bulk Register HCBULKCURRENTED 3.11 HC Head Bulk Register HCBULKHEADEDFigure 12. HC Head Bulk Register HCBULKHEADED Table 12. HC Head Bulk Register HCBULKHEADED Field Descriptions3.14 HC Frame Interval Register HCFMINTERVAL 3.13 HC Head Done Register HCDONEHEADFigure 14. HC Head Done Register HCDONEHEAD Table 14. HC Head Done Register HCDONEHEAD Field Descriptions3.16 HC Frame Number Register HCFMNUMBER 3.15 HC Frame Remaining Register HCFMREMAININGFigure 16. HC Frame Remaining Register HCFMREMAINING Figure 17. HC Frame Number Register HCFMNUMBERFigure 18. HC Periodic Start Register HCPERIODICSTART 3.17 HC Periodic Start Register HCPERIODICSTARTField ValueFigure 19. HC Low-Speed Threshold Register HCLSTHRESHOLD 3.18 HC Low-Speed Threshold Register HCLSTHRESHOLDRegisters FieldFigure 20. HC Root Hub A Register HCRHDESCRIPTORA 3.19 HC Root Hub A Register HCRHDESCRIPTORATable 20. HC Root Hub A Register HCRHDESCRIPTORA Field Descriptions FieldFigure 21. HC Root Hub B Register HCRHDESCRIPTORB 3.20 HC Root Hub B Register HCRHDESCRIPTORBTable 21. HC Root Hub B Register HCRHDESCRIPTORB Field Descriptions RegistersFigure 22. HC Root Hub Status Register HCRHSTATUS 3.21 HC Root Hub Status Register HCRHSTATUSTable 22. HC Root Hub Status Register HCRHSTATUS Field Descriptions FieldFigure 23. HC Port 1 Status and Control Register HCRHPORTSTATUS1 3.22 HC Port 1 Status and Control Register HCRHPORTSTATUS1Registers FieldField Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set theDescription Submit Documentation FeedbackFigure 24. HC Port 2 Status and Control Register HCRHPORTSTATUS2 3.23 HC Port 2 Status and Control Register HCRHPORTSTATUS2Registers FieldSubmit Documentation Feedback FieldDescription Applications IMPORTANT NOTICEProducts