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Texas Instruments TMS320C6747 DSP manual HC Current Control Register HCCONTROLCURRENTED, Field

Models: TMS320C6747 DSP

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3.10 HC Current Control Register (HCCONTROLCURRENTED)

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Registers

3.10 HC Current Control Register (HCCONTROLCURRENTED)

The HC current control register (HCCONTROLCURRENTED) defines the physical address of the next endpoint descriptor (ED) on the control ED list. HCCONTROLCURRENTED is shown in Figure 11 and described in Table 11.

Figure 11. HC Current Control Register (HCCONTROLCURRENTED)

31			16
	CCED
	R/W-0
15	4	3	0
CCED			Reserved
R/W-0			R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 11. HC Current Control Register (HCCONTROLCURRENTED) Field Descriptions

Bit	Field	Value	Description
31-4	CCED	0-FFF FFFFh	Physical address of the current ED on the control ED list. This field represents bits 31-4 of the
			physical address of the next ED on the control ED list. EDs are assumed to begin on a 16-byte
			aligned address, so bits 3-0 of this pointer are assumed to be 0. For the restrictions on physical
			addresses, see Section 2.7.
			A value of 0 indicates that the USB host controller has reached the end of the control ED list
			without finding any transfers to process. This register is automatically updated by the USB host
			controller.
3-0	Reserved	0	Reserved

SPRUFM8–September 2008	Universal Serial Bus OHCI Host Controller	21
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Texas Instruments TMS320C6747 DSP manual HC Current Control Register HCCONTROLCURRENTED, Field, Description

Contents

TMS320C6747 DSP Universal Serial Bus USB OHCI Host Controller Users GuideSubmit Documentation Feedback SPRUFM8-SeptemberContents List of Figures List of Tables USB Host Controller RegistersHC HCAA Address Register HCHCCA Field Descriptions Preface Read This FirstAbout This Manual Notational ConventionsUsers Guide Universal Serial Bus OHCI Host Controller1 Introduction 1.1 Purpose of the Peripheral2.1.2 USB1 Module Local Bus Clock and Local Reset 2.1 USB1 Module Clock and Reset2 Architecture 2.1.1 Internal System Bus Clocks Needed by the USB1 Module2.3.1 Power Switching Output Pins Not Supported 2.3 USB1 Module Differences From OHCI Specification for USB2.3.2 Overcurrent Protection Input Pins Not Supported 2.2 USB1 Module Open Host Controller Interface Functionality2.4 Implementation of OHCI Specification for USB 2.4.1 USB Host Controller Endpoint Descriptor ED List Head Pointers2.4.2 OHCI USB Suspend State 2.5 OHCI Interrupts 2.6 USB Host Controller Access to System Memory2.7 Physical Addressing Figure 1. Relationships Between Virtual Address Physical AddressTable 1. USB Host Controller Registers 3 RegistersFigure 3. HC Operating Mode Register HCCONTROL 3.2 HC Operating Mode Register HCCONTROL3.1 OHCI Revision Number Register HCREVISION Figure 2. OHCI Revision Number Register HCREVISIONField Table 3. HC Operating Mode Register HCCONTROL Field DescriptionsValue DescriptionFigure 4. HC Command and Status Register HCCOMMANDSTATUS 3.3 HC Command and Status Register HCCOMMANDSTATUSField ValueFigure 5. HC Interrupt and Status Register HCINTERRUPTSTATUS 3.4 HC Interrupt and Status Register HCINTERRUPTSTATUSRegisters FieldFigure 6. HC Interrupt Enable Register HCINTERRUPTENABLE 3.5 HC Interrupt Enable Register HCINTERRUPTENABLEField Value DescriptionFigure 7. HC Interrupt Disable Register HCINTERRUPTDISABLE 3.6 HC Interrupt Disable Register HCINTERRUPTDISABLERegisters Field3.8 HC Current Periodic Register HCPERIODCURRENTED 3.7 HC HCAA Address Register HCHCCAFigure 8. HC HCAA Address Register HCHCCA Table 8. HC HCAA Address Register HCHCCA Field DescriptionsFigure 10. HC Head Control Register HCCONTROLHEADED 3.9 HC Head Control Register HCCONTROLHEADEDTable 10. HC Head Control Register HCCONTROLHEADED Field Descriptions RegistersFigure 11. HC Current Control Register HCCONTROLCURRENTED 3.10 HC Current Control Register HCCONTROLCURRENTEDField Description3.12 HC Current Bulk Register HCBULKCURRENTED 3.11 HC Head Bulk Register HCBULKHEADEDFigure 12. HC Head Bulk Register HCBULKHEADED Table 12. HC Head Bulk Register HCBULKHEADED Field Descriptions3.14 HC Frame Interval Register HCFMINTERVAL 3.13 HC Head Done Register HCDONEHEADFigure 14. HC Head Done Register HCDONEHEAD Table 14. HC Head Done Register HCDONEHEAD Field Descriptions3.16 HC Frame Number Register HCFMNUMBER 3.15 HC Frame Remaining Register HCFMREMAININGFigure 16. HC Frame Remaining Register HCFMREMAINING Figure 17. HC Frame Number Register HCFMNUMBERFigure 18. HC Periodic Start Register HCPERIODICSTART 3.17 HC Periodic Start Register HCPERIODICSTARTField ValueFigure 19. HC Low-Speed Threshold Register HCLSTHRESHOLD 3.18 HC Low-Speed Threshold Register HCLSTHRESHOLDRegisters FieldFigure 20. HC Root Hub A Register HCRHDESCRIPTORA 3.19 HC Root Hub A Register HCRHDESCRIPTORATable 20. HC Root Hub A Register HCRHDESCRIPTORA Field Descriptions FieldFigure 21. HC Root Hub B Register HCRHDESCRIPTORB 3.20 HC Root Hub B Register HCRHDESCRIPTORBTable 21. HC Root Hub B Register HCRHDESCRIPTORB Field Descriptions RegistersFigure 22. HC Root Hub Status Register HCRHSTATUS 3.21 HC Root Hub Status Register HCRHSTATUSTable 22. HC Root Hub Status Register HCRHSTATUS Field Descriptions FieldFigure 23. HC Port 1 Status and Control Register HCRHPORTSTATUS1 3.22 HC Port 1 Status and Control Register HCRHPORTSTATUS1Registers FieldField Port 1 port power status/set port power. The host controller driver can write a 1 to this bit to set theDescription Submit Documentation FeedbackFigure 24. HC Port 2 Status and Control Register HCRHPORTSTATUS2 3.23 HC Port 2 Status and Control Register HCRHPORTSTATUS2Registers FieldField DescriptionSubmit Documentation Feedback IMPORTANT NOTICE ProductsApplications